Power Estimation for IP-Based Modules
In this paper, we propose a power estimation technique for register transfer level model of digital circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components based on the statistical knowledge of their primary inputs/outputs. During power estimation p...
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| creator | Durrani, Y.A. Riesgo, T. |
| description | In this paper, we propose a power estimation technique for register transfer level model of digital circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components based on the statistical knowledge of their primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero delay simulation is performed and the power dissipation is predicted by a macromodel function. In experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of 1.84%. Our model provides accurate power estimation |
| doi_str_mv | 10.1109/ISSOC.2006.321976 |
| format | Conference Proceeding |
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Our model provides accurate power estimation</description><subject>Circuit simulation</subject><subject>Computational modeling</subject><subject>Digital circuits</subject><subject>Electronics industry</subject><subject>Interpolation</subject><subject>Power dissipation</subject><subject>Power generation</subject><subject>Registers</subject><subject>Statistics</subject><subject>Table lookup</subject><isbn>1424406218</isbn><isbn>9781424406210</isbn><isbn>1424406226</isbn><isbn>9781424406227</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFjsFKxDAURSMiqDPzAeKmG5et7yUvL8lSy4wWZpiBuh_SJoXKaKWpiH9vQcGzuZzN5Qhxg1Aggruv6npfFhKACyXRGT4T10iSCFhKPv8XtJdildIrzCjHypkrcXcYvuKYrdPUv_mpH96zbhiz6pA_-hRDthvC5ymmpbjo_CnF1d8uRL1Zv5TP-Xb_VJUP27x3MOWW0GsfrY0mWtPqxnjwMhA4cI2eE8g6Cp2VEDQZ9kzIbaPaII3uFKqFuP197WOMx49xLhq_j4TIxKR-AH-rPek</recordid><startdate>200611</startdate><enddate>200611</enddate><creator>Durrani, Y.A.</creator><creator>Riesgo, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200611</creationdate><title>Power Estimation for IP-Based Modules</title><author>Durrani, Y.A. ; Riesgo, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-841a5ae88e7e87c5b7a0a2d40909b54404894df820d5476a6416cb3cd275f313</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Circuit simulation</topic><topic>Computational modeling</topic><topic>Digital circuits</topic><topic>Electronics industry</topic><topic>Interpolation</topic><topic>Power dissipation</topic><topic>Power generation</topic><topic>Registers</topic><topic>Statistics</topic><topic>Table lookup</topic><toplevel>online_resources</toplevel><creatorcontrib>Durrani, Y.A.</creatorcontrib><creatorcontrib>Riesgo, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Durrani, Y.A.</au><au>Riesgo, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Power Estimation for IP-Based Modules</atitle><btitle>2006 International Symposium on System-on-Chip</btitle><stitle>ISSOC</stitle><date>2006-11</date><risdate>2006</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>1424406218</isbn><isbn>9781424406210</isbn><eisbn>1424406226</eisbn><eisbn>9781424406227</eisbn><abstract>In this paper, we propose a power estimation technique for register transfer level model of digital circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components based on the statistical knowledge of their primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero delay simulation is performed and the power dissipation is predicted by a macromodel function. In experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of 1.84%. Our model provides accurate power estimation</abstract><pub>IEEE</pub><doi>10.1109/ISSOC.2006.321976</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation Computational modeling Digital circuits Electronics industry Interpolation Power dissipation Power generation Registers Statistics Table lookup |
| title | Power Estimation for IP-Based Modules |
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