A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer
A frequency digitizer based on a continuous time delta-sigma PLL is presented. The architecture combines the demodulation and digitization process of a frequency modulated signal. This operation is done at a high IF frequency with an excellent accuracy thanks to the oversampling nature of the loop....
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| creator | Sharifkhani, M. Sachdev, M. |
| description | A frequency digitizer based on a continuous time delta-sigma PLL is presented. The architecture combines the demodulation and digitization process of a frequency modulated signal. This operation is done at a high IF frequency with an excellent accuracy thanks to the oversampling nature of the loop. Since the digitization occurs in phase domain, the power consumption of the digitizer drops significantly compared to the amplitude domain digitizers operating at the same frequency. In addition, owing to its high dynamic range, the digitizer can easily accommodate the frequency drift and DC offset that exist in the wireless environment. The design is implemented in a 0.18 μm CMOS technology. It operates at 128MHz carrier frequency and consumes 6.5 mW. |
| doi_str_mv | 10.1109/CICC.2006.320911 |
| format | Conference Proceeding |
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The architecture combines the demodulation and digitization process of a frequency modulated signal. This operation is done at a high IF frequency with an excellent accuracy thanks to the oversampling nature of the loop. Since the digitization occurs in phase domain, the power consumption of the digitizer drops significantly compared to the amplitude domain digitizers operating at the same frequency. In addition, owing to its high dynamic range, the digitizer can easily accommodate the frequency drift and DC offset that exist in the wireless environment. The design is implemented in a 0.18 μm CMOS technology. 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The architecture combines the demodulation and digitization process of a frequency modulated signal. This operation is done at a high IF frequency with an excellent accuracy thanks to the oversampling nature of the loop. Since the digitization occurs in phase domain, the power consumption of the digitizer drops significantly compared to the amplitude domain digitizers operating at the same frequency. In addition, owing to its high dynamic range, the digitizer can easily accommodate the frequency drift and DC offset that exist in the wireless environment. The design is implemented in a 0.18 μm CMOS technology. It operates at 128MHz carrier frequency and consumes 6.5 mW.</description><subject>Circuits</subject><subject>Demodulation</subject><subject>Energy consumption</subject><subject>Feedback loop</subject><subject>Frequency conversion</subject><subject>Phase frequency detector</subject><subject>Phase locked loops</subject><subject>Sampling methods</subject><subject>Signal processing</subject><subject>Voltage-controlled oscillators</subject><issn>0886-5930</issn><issn>2152-3630</issn><isbn>1424400759</isbn><isbn>9781424400751</isbn><isbn>1424400767</isbn><isbn>9781424400768</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9yT1uwjAUAODHn0Qo3ZG6-AIO79lOiEdkitqpDOwogtfWqHHAJgM9R2_Q-3CmLpW6dfqGD2BGmBOhnbtn53KFWOZaoSXqwYSMMgZxUS76kCkqlNSlxsFfFHYIGVZVKQurcQyTlI6IZG2lMlguxea9TixXbVP7IFwbLj50bZfk1jcsVDjIl3jgKG5ft2-xjnzuOOyvYuXf_MV_cpzC6LX-SHz_6x08rB-37kl6Zt6dom_qeN0ZImMN6v_3BzjBPlE</recordid><startdate>200609</startdate><enddate>200609</enddate><creator>Sharifkhani, M.</creator><creator>Sachdev, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200609</creationdate><title>A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer</title><author>Sharifkhani, M. ; Sachdev, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_41149403</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Circuits</topic><topic>Demodulation</topic><topic>Energy consumption</topic><topic>Feedback loop</topic><topic>Frequency conversion</topic><topic>Phase frequency detector</topic><topic>Phase locked loops</topic><topic>Sampling methods</topic><topic>Signal processing</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Sharifkhani, M.</creatorcontrib><creatorcontrib>Sachdev, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sharifkhani, M.</au><au>Sachdev, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer</atitle><btitle>IEEE Custom Integrated Circuits Conference 2006</btitle><stitle>CICC</stitle><date>2006-09</date><risdate>2006</risdate><spage>205</spage><epage>208</epage><pages>205-208</pages><issn>0886-5930</issn><eissn>2152-3630</eissn><isbn>1424400759</isbn><isbn>9781424400751</isbn><eisbn>1424400767</eisbn><eisbn>9781424400768</eisbn><abstract>A frequency digitizer based on a continuous time delta-sigma PLL is presented. The architecture combines the demodulation and digitization process of a frequency modulated signal. This operation is done at a high IF frequency with an excellent accuracy thanks to the oversampling nature of the loop. Since the digitization occurs in phase domain, the power consumption of the digitizer drops significantly compared to the amplitude domain digitizers operating at the same frequency. In addition, owing to its high dynamic range, the digitizer can easily accommodate the frequency drift and DC offset that exist in the wireless environment. The design is implemented in a 0.18 μm CMOS technology. It operates at 128MHz carrier frequency and consumes 6.5 mW.</abstract><pub>IEEE</pub><doi>10.1109/CICC.2006.320911</doi></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Demodulation Energy consumption Feedback loop Frequency conversion Phase frequency detector Phase locked loops Sampling methods Signal processing Voltage-controlled oscillators |
| title | A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer |
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