Floating-Point Divider Design for FPGAs

Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right bal...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2007-01, Vol.15 (1), p.115-118
Hauptverfasser: Hemmert, K.S., Underwood, K.D.
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Underwood, K.D.
description Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11 FPGA, the range includes 250-MHz IEEE compliant double precision divides that are fully pipelined to 187-MHz iterative cores. Similarly, area requirements range from 4100 slices down to a mere 334 slices
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source IEEE Electronic Library (IEL)
subjects Applied sciences
Circuit properties
Clocks
Delay
Design engineering
Design. Technologies. Operation analysis. Testing
Digital circuits
Divider
Dividers
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Field programmable gate arrays
field-programmable gate array (FPGA)
Floating point arithmetic
floating-point
Gate arrays
IEEE-754
Integrated circuits
Integrated circuits by function (including memories and processors)
Iterative algorithms
Microprocessors
Pipelines
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Space technology
Throughput
Very large scale integration
title Floating-Point Divider Design for FPGAs
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