Floating-Point Divider Design for FPGAs
Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right bal...
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Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2007-01, Vol.15 (1), p.115-118 |
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container_title | IEEE transactions on very large scale integration (VLSI) systems |
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creator | Hemmert, K.S. Underwood, K.D. |
description | Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11 FPGA, the range includes 250-MHz IEEE compliant double precision divides that are fully pipelined to 187-MHz iterative cores. Similarly, area requirements range from 4100 slices down to a mere 334 slices |
doi_str_mv | 10.1109/TVLSI.2007.891099 |
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fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_4114363</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4114363</ieee_id><sourcerecordid>2544979351</sourcerecordid><originalsourceid>FETCH-LOGICAL-c385t-c78e3ac4504affacd2d5dd40c5a6ff8826e417e1ece6b3bb90fd631fdaad5f703</originalsourceid><addsrcrecordid>eNp9kE1LAzEQhoMoWKs_QLwsgnrammw-NjmW1tZCwYLVa0jzUVK2uzXZCv570w8UPDiXGWaeeZl5AbhGsIcQFI_z9-nrpFdAWPa4SA1xAjqI0jIXKU5TDRnOeYHgObiIcQUhIkTADngYVY1qfb3MZ42v22zoP72xIRva6Jd15pqQjWbjfrwEZ05V0V4dcxe8jZ7mg-d8-jKeDPrTXGNO21yX3GKlCYVEOae0KQw1hkBNFXOO84JZgkqLrLZsgRcLAZ1hGDmjlKGuhLibLtrrbkLzsbWxlWsfta0qVdtmGyUXDHHOaJnI-39JTCjHJRQJvP0DrpptqNMXUqCioJgmsAvQAdKhiTFYJzfBr1X4kgjKncNy77DcOSwPDqedu6OwilpVLqha-_i7yJOuYDvtmwPnrbU_Y4IQwQzjbwfnguo</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912253558</pqid></control><display><type>article</type><title>Floating-Point Divider Design for FPGAs</title><source>IEEE Electronic Library (IEL)</source><creator>Hemmert, K.S. ; Underwood, K.D.</creator><creatorcontrib>Hemmert, K.S. ; Underwood, K.D.</creatorcontrib><description>Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11 FPGA, the range includes 250-MHz IEEE compliant double precision divides that are fully pipelined to 187-MHz iterative cores. Similarly, area requirements range from 4100 slices down to a mere 334 slices</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2007.891099</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Applied sciences ; Circuit properties ; Clocks ; Delay ; Design engineering ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Divider ; Dividers ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Field programmable gate arrays ; field-programmable gate array (FPGA) ; Floating point arithmetic ; floating-point ; Gate arrays ; IEEE-754 ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Iterative algorithms ; Microprocessors ; Pipelines ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Space technology ; Throughput ; Very large scale integration</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2007-01, Vol.15 (1), p.115-118</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2007</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c385t-c78e3ac4504affacd2d5dd40c5a6ff8826e417e1ece6b3bb90fd631fdaad5f703</citedby><cites>FETCH-LOGICAL-c385t-c78e3ac4504affacd2d5dd40c5a6ff8826e417e1ece6b3bb90fd631fdaad5f703</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4114363$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,778,782,794,4012,27906,27907,27908,54741</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4114363$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18583968$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Hemmert, K.S.</creatorcontrib><creatorcontrib>Underwood, K.D.</creatorcontrib><title>Floating-Point Divider Design for FPGAs</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11 FPGA, the range includes 250-MHz IEEE compliant double precision divides that are fully pipelined to 187-MHz iterative cores. Similarly, area requirements range from 4100 slices down to a mere 334 slices</description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Clocks</subject><subject>Delay</subject><subject>Design engineering</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Divider</subject><subject>Dividers</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Field programmable gate arrays</subject><subject>field-programmable gate array (FPGA)</subject><subject>Floating point arithmetic</subject><subject>floating-point</subject><subject>Gate arrays</subject><subject>IEEE-754</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Iterative algorithms</subject><subject>Microprocessors</subject><subject>Pipelines</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Space technology</subject><subject>Throughput</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kE1LAzEQhoMoWKs_QLwsgnrammw-NjmW1tZCwYLVa0jzUVK2uzXZCv570w8UPDiXGWaeeZl5AbhGsIcQFI_z9-nrpFdAWPa4SA1xAjqI0jIXKU5TDRnOeYHgObiIcQUhIkTADngYVY1qfb3MZ42v22zoP72xIRva6Jd15pqQjWbjfrwEZ05V0V4dcxe8jZ7mg-d8-jKeDPrTXGNO21yX3GKlCYVEOae0KQw1hkBNFXOO84JZgkqLrLZsgRcLAZ1hGDmjlKGuhLibLtrrbkLzsbWxlWsfta0qVdtmGyUXDHHOaJnI-39JTCjHJRQJvP0DrpptqNMXUqCioJgmsAvQAdKhiTFYJzfBr1X4kgjKncNy77DcOSwPDqedu6OwilpVLqha-_i7yJOuYDvtmwPnrbU_Y4IQwQzjbwfnguo</recordid><startdate>200701</startdate><enddate>200701</enddate><creator>Hemmert, K.S.</creator><creator>Underwood, K.D.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>200701</creationdate><title>Floating-Point Divider Design for FPGAs</title><author>Hemmert, K.S. ; Underwood, K.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c385t-c78e3ac4504affacd2d5dd40c5a6ff8826e417e1ece6b3bb90fd631fdaad5f703</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Clocks</topic><topic>Delay</topic><topic>Design engineering</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Divider</topic><topic>Dividers</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Field programmable gate arrays</topic><topic>field-programmable gate array (FPGA)</topic><topic>Floating point arithmetic</topic><topic>floating-point</topic><topic>Gate arrays</topic><topic>IEEE-754</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Iterative algorithms</topic><topic>Microprocessors</topic><topic>Pipelines</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Space technology</topic><topic>Throughput</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hemmert, K.S.</creatorcontrib><creatorcontrib>Underwood, K.D.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hemmert, K.S.</au><au>Underwood, K.D.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Floating-Point Divider Design for FPGAs</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2007-01</date><risdate>2007</risdate><volume>15</volume><issue>1</issue><spage>115</spage><epage>118</epage><pages>115-118</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11 FPGA, the range includes 250-MHz IEEE compliant double precision divides that are fully pipelined to 187-MHz iterative cores. Similarly, area requirements range from 4100 slices down to a mere 334 slices</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2007.891099</doi><tpages>4</tpages></addata></record> |
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subjects | Applied sciences Circuit properties Clocks Delay Design engineering Design. Technologies. Operation analysis. Testing Digital circuits Divider Dividers Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Field programmable gate arrays field-programmable gate array (FPGA) Floating point arithmetic floating-point Gate arrays IEEE-754 Integrated circuits Integrated circuits by function (including memories and processors) Iterative algorithms Microprocessors Pipelines Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Space technology Throughput Very large scale integration |
title | Floating-Point Divider Design for FPGAs |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T04%3A36%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Floating-Point%20Divider%20Design%20for%20FPGAs&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Hemmert,%20K.S.&rft.date=2007-01&rft.volume=15&rft.issue=1&rft.spage=115&rft.epage=118&rft.pages=115-118&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2007.891099&rft_dat=%3Cproquest_RIE%3E2544979351%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=912253558&rft_id=info:pmid/&rft_ieee_id=4114363&rfr_iscdi=true |