EMC Assessment at Chip and PCB Level: Use of the ICEM Model for Jitter Analysis in an Integrated PLL
This paper deals with the use of the integrated circuit electromagnetic model (ICEM) to analyze, predict, and optimize autocompatibility and electromagnetic emission at chip and system level. ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a p...
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| Veröffentlicht in: | IEEE transactions on electromagnetic compatibility 2007-02, Vol.49 (1), p.182-191 |
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| container_title | IEEE transactions on electromagnetic compatibility |
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| creator | Levant, J.-L. Ramdani, M. Perdriau, R. Drissi, M. |
| description | This paper deals with the use of the integrated circuit electromagnetic model (ICEM) to analyze, predict, and optimize autocompatibility and electromagnetic emission at chip and system level. ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a power distribution network model and an internal current source modeling digital activity. Such an approach enables the description of any kind of digital or mixed-signal design. This model is useful either for the IC manufacturer or the system manufacturer. The power distribution network of a printed circuit board (PCB) can be optimized using this model by choosing the number and the right values of decoupling capacitors as well as the size of power planes. The IC manufacturer may check out the autocompatibility of an IC and determine the number of power pins as well as the package to be used. As an example, jitter analysis of an integrated phase-locked-loop can be performed using ICEM. This paper demonstrates that this jitter can be predicted by simulation and that corrective solutions can be provided and checked out before implementation |
| doi_str_mv | 10.1109/TEMC.2006.888181 |
| format | Article |
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ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a power distribution network model and an internal current source modeling digital activity. Such an approach enables the description of any kind of digital or mixed-signal design. This model is useful either for the IC manufacturer or the system manufacturer. The power distribution network of a printed circuit board (PCB) can be optimized using this model by choosing the number and the right values of decoupling capacitors as well as the size of power planes. The IC manufacturer may check out the autocompatibility of an IC and determine the number of power pins as well as the package to be used. As an example, jitter analysis of an integrated phase-locked-loop can be performed using ICEM. This paper demonstrates that this jitter can be predicted by simulation and that corrective solutions can be provided and checked out before implementation</description><identifier>ISSN: 0018-9375</identifier><identifier>EISSN: 1558-187X</identifier><identifier>DOI: 10.1109/TEMC.2006.888181</identifier><identifier>CODEN: IEMCAE</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Application specific integrated circuit (ASIC) ; Applied sciences ; Chips ; Circuit boards ; Circuit properties ; Circuits of signal characteristics conditioning (including delay circuits) ; decoupling ; Design. Technologies. Operation analysis. Testing ; Digital ; Electric, optical and optoelectronic circuits ; Electromagnetic compatibility ; Electronic circuits ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; Information, signal and communications theory ; integrated circuit electromagnetic model (ICEM) ; Integrated circuits ; Jitter ; Mathematical models ; modeling ; Networks ; phase-locked-loop (PLL) ; prediction ; Printed circuit boards ; Printed circuits ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; simulation ; Studies ; Telecommunications and information theory</subject><ispartof>IEEE transactions on electromagnetic compatibility, 2007-02, Vol.49 (1), p.182-191</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a power distribution network model and an internal current source modeling digital activity. Such an approach enables the description of any kind of digital or mixed-signal design. This model is useful either for the IC manufacturer or the system manufacturer. The power distribution network of a printed circuit board (PCB) can be optimized using this model by choosing the number and the right values of decoupling capacitors as well as the size of power planes. The IC manufacturer may check out the autocompatibility of an IC and determine the number of power pins as well as the package to be used. As an example, jitter analysis of an integrated phase-locked-loop can be performed using ICEM. This paper demonstrates that this jitter can be predicted by simulation and that corrective solutions can be provided and checked out before implementation</description><subject>Application specific integrated circuit (ASIC)</subject><subject>Applied sciences</subject><subject>Chips</subject><subject>Circuit boards</subject><subject>Circuit properties</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>decoupling</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electromagnetic compatibility</subject><subject>Electronic circuits</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Information, signal and communications theory</subject><subject>integrated circuit electromagnetic model (ICEM)</subject><subject>Integrated circuits</subject><subject>Jitter</subject><subject>Mathematical models</subject><subject>modeling</subject><subject>Networks</subject><subject>phase-locked-loop (PLL)</subject><subject>prediction</subject><subject>Printed circuit boards</subject><subject>Printed circuits</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>simulation</subject><subject>Studies</subject><subject>Telecommunications and information theory</subject><issn>0018-9375</issn><issn>1558-187X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kc1r3DAQxUVpoNuk90IvotCWHrzVWJ_ubWs2zRYv7SGB3oRij7oOXnsjeQP57yPjkEAOBYHQ6PfeDPMIeQ9sCcCKb5frbbnMGVNLYwwYeEUWIKXJwOi_r8mCMTBZwbV8Q97GeJOeQuZ8QZoko6sYMcY99iN1Iy137YG6vqF_yh-0wjvsvtOriHTwdNwh3ZTrLd0ODXbUD4H-ascRA131rruPbaRtn7R004_4L7gRk0tVnZET77qI7x7vU3J1vr4sL7Lq989NuaqyWhg-Ztp4DxyKXAkwTOVK1qCKBr0rhL52wFWja8ULMJinSsMK1kgN_loUTuVNzU_J19l35zp7CO3ehXs7uNZerCo71RgT3OTG3EFiv8zsIQy3R4yj3bexxq5zPQ7HaI2WTLAcikR-_i_JhWI6nQR-fAHeDMeQFpPc1NRXM5UgNkN1GGIM6J8GBWanJO2UpJ2StHOSSfLp0dfF2nU-uL5u47POSCmFngb9MHMtIj59C2AqbYo_AAyHoTs</recordid><startdate>20070201</startdate><enddate>20070201</enddate><creator>Levant, J.-L.</creator><creator>Ramdani, M.</creator><creator>Perdriau, R.</creator><creator>Drissi, M.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Technologies. Operation analysis. Testing</topic><topic>Digital</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electromagnetic compatibility</topic><topic>Electronic circuits</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Information, signal and communications theory</topic><topic>integrated circuit electromagnetic model (ICEM)</topic><topic>Integrated circuits</topic><topic>Jitter</topic><topic>Mathematical models</topic><topic>modeling</topic><topic>Networks</topic><topic>phase-locked-loop (PLL)</topic><topic>prediction</topic><topic>Printed circuit boards</topic><topic>Printed circuits</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>simulation</topic><topic>Studies</topic><topic>Telecommunications and information theory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Levant, J.-L.</creatorcontrib><creatorcontrib>Ramdani, M.</creatorcontrib><creatorcontrib>Perdriau, R.</creatorcontrib><creatorcontrib>Drissi, M.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Hyper Article en Ligne (HAL)</collection><jtitle>IEEE transactions on electromagnetic compatibility</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Levant, J.-L.</au><au>Ramdani, M.</au><au>Perdriau, R.</au><au>Drissi, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>EMC Assessment at Chip and PCB Level: Use of the ICEM Model for Jitter Analysis in an Integrated PLL</atitle><jtitle>IEEE transactions on electromagnetic compatibility</jtitle><stitle>TEMC</stitle><date>2007-02-01</date><risdate>2007</risdate><volume>49</volume><issue>1</issue><spage>182</spage><epage>191</epage><pages>182-191</pages><issn>0018-9375</issn><eissn>1558-187X</eissn><coden>IEMCAE</coden><abstract>This paper deals with the use of the integrated circuit electromagnetic model (ICEM) to analyze, predict, and optimize autocompatibility and electromagnetic emission at chip and system level. ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a power distribution network model and an internal current source modeling digital activity. Such an approach enables the description of any kind of digital or mixed-signal design. This model is useful either for the IC manufacturer or the system manufacturer. The power distribution network of a printed circuit board (PCB) can be optimized using this model by choosing the number and the right values of decoupling capacitors as well as the size of power planes. The IC manufacturer may check out the autocompatibility of an IC and determine the number of power pins as well as the package to be used. As an example, jitter analysis of an integrated phase-locked-loop can be performed using ICEM. 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| ispartof | IEEE transactions on electromagnetic compatibility, 2007-02, Vol.49 (1), p.182-191 |
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| subjects | Application specific integrated circuit (ASIC) Applied sciences Chips Circuit boards Circuit properties Circuits of signal characteristics conditioning (including delay circuits) decoupling Design. Technologies. Operation analysis. Testing Digital Electric, optical and optoelectronic circuits Electromagnetic compatibility Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Information, signal and communications theory integrated circuit electromagnetic model (ICEM) Integrated circuits Jitter Mathematical models modeling Networks phase-locked-loop (PLL) prediction Printed circuit boards Printed circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices simulation Studies Telecommunications and information theory |
| title | EMC Assessment at Chip and PCB Level: Use of the ICEM Model for Jitter Analysis in an Integrated PLL |
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