A Wide Operating Frequency Range Delay-Locked Loop Using a Recursive D/A Converter
A wide operating frequency range, false-lock free delay-locked loop with mixed-mode calibration is presented. The recursive D/A converter in the auxiliary circuit expands the operating frequency range with minimum hardware by controlling the capacitive loading of a delay cell. Moreover, the sampling...
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creator | Byong-Chan Lim In-Joon Jo Dong-Soo Park Kuk-Tae Hong |
description | A wide operating frequency range, false-lock free delay-locked loop with mixed-mode calibration is presented. The recursive D/A converter in the auxiliary circuit expands the operating frequency range with minimum hardware by controlling the capacitive loading of a delay cell. Moreover, the sampling phase detector with the D/A converter automatically tracks the false-lock free condition. The proposed DLL with equally spaced 14-phase clock outputs is implemented in 0.18-mum, 3.3V digital CMOS process, and its operating frequency ranges from 15MHz to 270MHz. The measured peak-to-peak jitter and rms jitter at 270MHz are 33.3psec and 3.93psec, respectively. The DLL occupies 0.22mm 2 and consumes 19mA |
doi_str_mv | 10.1109/ESSCIR.2006.307479 |
format | Conference Proceeding |
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The recursive D/A converter in the auxiliary circuit expands the operating frequency range with minimum hardware by controlling the capacitive loading of a delay cell. Moreover, the sampling phase detector with the D/A converter automatically tracks the false-lock free condition. The proposed DLL with equally spaced 14-phase clock outputs is implemented in 0.18-mum, 3.3V digital CMOS process, and its operating frequency ranges from 15MHz to 270MHz. The measured peak-to-peak jitter and rms jitter at 270MHz are 33.3psec and 3.93psec, respectively. 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The recursive D/A converter in the auxiliary circuit expands the operating frequency range with minimum hardware by controlling the capacitive loading of a delay cell. Moreover, the sampling phase detector with the D/A converter automatically tracks the false-lock free condition. The proposed DLL with equally spaced 14-phase clock outputs is implemented in 0.18-mum, 3.3V digital CMOS process, and its operating frequency ranges from 15MHz to 270MHz. The measured peak-to-peak jitter and rms jitter at 270MHz are 33.3psec and 3.93psec, respectively. The DLL occupies 0.22mm 2 and consumes 19mA</description><subject>Calibration</subject><subject>Circuits</subject><subject>Delay</subject><subject>Detectors</subject><subject>Frequency conversion</subject><subject>Frequency locked loops</subject><subject>Hardware</subject><subject>Jitter</subject><subject>Phase detection</subject><subject>Sampling methods</subject><issn>1930-8833</issn><issn>2643-1319</issn><isbn>9781424403035</isbn><isbn>1424403022</isbn><isbn>9781424403028</isbn><isbn>1424403030</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjMtqwkAUQIc-oGLzA-1mfiB6Z-5kHsuQqhUCQqx0KcPkRtLaxE5U8O9raVdncQ6HsScBEyHATWfrdbGsJhJATxCMMu6GjaRWmAoU7pYlzlihpFKAgNkdGwmHkFqL-MCSYfgAAGG0Ei4bsSrn721NfHWg6I9tt-PzSN8n6sKFV77bEX-hvb-kZR8-qeZl3x_4ZvjtPK8onOLQnq_NNOdF350pHik-svvG7wdK_jlmm_nsrXhNy9ViWeRl2gqTHdNGGSTS3qBTmXXaENqgAZtgMSOwXqlaXkXtfSaVszII8E0AK72xvtY4Zs9_35aItofYfvl42SpwzoLEH0r8UPI</recordid><startdate>200609</startdate><enddate>200609</enddate><creator>Byong-Chan Lim</creator><creator>In-Joon Jo</creator><creator>Dong-Soo Park</creator><creator>Kuk-Tae Hong</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200609</creationdate><title>A Wide Operating Frequency Range Delay-Locked Loop Using a Recursive D/A Converter</title><author>Byong-Chan Lim ; In-Joon Jo ; Dong-Soo Park ; Kuk-Tae Hong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f473ee6a739458967e38c603fc835e08a44d2589daa524982c10afc082a78ad63</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Calibration</topic><topic>Circuits</topic><topic>Delay</topic><topic>Detectors</topic><topic>Frequency conversion</topic><topic>Frequency locked loops</topic><topic>Hardware</topic><topic>Jitter</topic><topic>Phase detection</topic><topic>Sampling methods</topic><toplevel>online_resources</toplevel><creatorcontrib>Byong-Chan Lim</creatorcontrib><creatorcontrib>In-Joon Jo</creatorcontrib><creatorcontrib>Dong-Soo Park</creatorcontrib><creatorcontrib>Kuk-Tae Hong</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Byong-Chan Lim</au><au>In-Joon Jo</au><au>Dong-Soo Park</au><au>Kuk-Tae Hong</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Wide Operating Frequency Range Delay-Locked Loop Using a Recursive D/A Converter</atitle><btitle>2006 Proceedings of the 32nd European Solid-State Circuits Conference</btitle><stitle>ESSCIR</stitle><date>2006-09</date><risdate>2006</risdate><spage>456</spage><epage>459</epage><pages>456-459</pages><issn>1930-8833</issn><eissn>2643-1319</eissn><isbn>9781424403035</isbn><isbn>1424403022</isbn><isbn>9781424403028</isbn><isbn>1424403030</isbn><abstract>A wide operating frequency range, false-lock free delay-locked loop with mixed-mode calibration is presented. The recursive D/A converter in the auxiliary circuit expands the operating frequency range with minimum hardware by controlling the capacitive loading of a delay cell. Moreover, the sampling phase detector with the D/A converter automatically tracks the false-lock free condition. The proposed DLL with equally spaced 14-phase clock outputs is implemented in 0.18-mum, 3.3V digital CMOS process, and its operating frequency ranges from 15MHz to 270MHz. The measured peak-to-peak jitter and rms jitter at 270MHz are 33.3psec and 3.93psec, respectively. The DLL occupies 0.22mm 2 and consumes 19mA</abstract><pub>IEEE</pub><doi>10.1109/ESSCIR.2006.307479</doi><tpages>4</tpages></addata></record> |
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identifier | ISSN: 1930-8833 |
ispartof | 2006 Proceedings of the 32nd European Solid-State Circuits Conference, 2006, p.456-459 |
issn | 1930-8833 2643-1319 |
language | eng |
recordid | cdi_ieee_primary_4099802 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Calibration Circuits Delay Detectors Frequency conversion Frequency locked loops Hardware Jitter Phase detection Sampling methods |
title | A Wide Operating Frequency Range Delay-Locked Loop Using a Recursive D/A Converter |
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