A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor

A fast 128-bit end-around carry adder is designed and fabricated as part of the POWER6 floating-point unit in a 65nm SOI process technology. Efficient use of static circuits and careful balance of the look-ahead tree enable our floating point design to operate beyond 5GHz with 1.1 V supply

Bibliographische Detailangaben

Hauptverfasser:	Xiao Yan Yu, Yiu-Hing Chan, Curran, B., Schwarz, E., Kelly, M., Fleischer, B.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders Circuits Delay Frequency Logic Microprocessors Modems Pipelines Space technology Timing
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