Low Power and High Speed Addition Strategies for VLSI
Very large scale integration (VLSI) adders are critically important in digital designs since they are utilized in ALUs, memory addressing, cryptography, and floating-point units. Since adders are often responsible for setting the minimum clock cycle time in a processor, they can be critical to any i...
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| creator | Stine, J.E. Grad, J. |
| description | Very large scale integration (VLSI) adders are critically important in digital designs since they are utilized in ALUs, memory addressing, cryptography, and floating-point units. Since adders are often responsible for setting the minimum clock cycle time in a processor, they can be critical to any improvements seen at the VLSI level. However, fast logarithmic time adders can be impractical for a given VLSI implementation due to their prohibitive structures in terms of interconnect congestion, delay, and power. This paper discusses several adder designs and their analysis in the sub-micron and nanometer range and gives recommendations for choosing the best architectures for high-speed and low-power dissipation |
| doi_str_mv | 10.1109/ICSICT.2006.306327 |
| format | Conference Proceeding |
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| language | eng |
| recordid | cdi_ieee_primary_4098488 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Adders CMOS logic circuits CMOS technology Computer architecture Delay estimation Design engineering Integrated circuit interconnections Logic design Space technology Very large scale integration |
| title | Low Power and High Speed Addition Strategies for VLSI |
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