A CMOS Low Voltage Charge Pump

Charge pump circuits are used for obtaining higher voltages than normal power supply voltage in flash memories, DRAMs and low voltage designs. In this paper, we present a charge pump circuit in standard CMOS technology that is suited for low voltage operation. Our proposed charge pump uses a cross-...

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Hauptverfasser: Bhalerao, S.A., Chaudhary, A.V., Patrikar, R.M.
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Chaudhary, A.V.
Patrikar, R.M.
description Charge pump circuits are used for obtaining higher voltages than normal power supply voltage in flash memories, DRAMs and low voltage designs. In this paper, we present a charge pump circuit in standard CMOS technology that is suited for low voltage operation. Our proposed charge pump uses a cross- connected NMOS cell as the basic element and PMOS switches are employed to connect one stage to the next. The simulated output voltages of the proposed 4 stage charge pump for input voltage of 0.9 V, 1.2 V, 1.5 V, 1.8 V and 2.1 V are 3.9 V, 5.1 V, 6.35 V, 7.51 V and 8.4 V respectively. This proposed charge pump is suitable for low power CMOS mixed-mode designs.
doi_str_mv 10.1109/VLSID.2007.9
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identifier ISSN: 1063-9667
ispartof 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007, p.941-946
issn 1063-9667
2380-6923
language eng
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Capacitors
Charge pumps
Circuits
Clocks
CMOS technology
Diodes
Low voltage
MOS devices
Power supplies
Switches
title A CMOS Low Voltage Charge Pump
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