MTNET: Design and Optimization of a Wireless SOC Test Framework
This paper focuses on a novel self-configurable multihop wireless on-chip micronetwork, namely MTNet, to serve as the test access architecture for testing next generation billion-transistor SoCs. A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Furt...
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| creator | Dan Zhao Yi Wang |
| description | This paper focuses on a novel self-configurable multihop wireless on-chip micronetwork, namely MTNet, to serve as the test access architecture for testing next generation billion-transistor SoCs. A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Further, a path driven test scheduling algorithm is developed to design and optimize the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of using MTNet for nanoscale SoC testing. |
| doi_str_mv | 10.1109/SOCC.2006.283889 |
| format | Conference Proceeding |
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A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Further, a path driven test scheduling algorithm is developed to design and optimize the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of using MTNet for nanoscale SoC testing.</description><subject>Automatic testing</subject><subject>Communication system control</subject><subject>Costs</subject><subject>Design optimization</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuit technology</subject><subject>Job shop scheduling</subject><subject>Network-on-a-chip</subject><subject>Radio frequency</subject><subject>Routing</subject><issn>2164-1676</issn><issn>2164-1706</issn><isbn>0780397819</isbn><isbn>9780780397811</isbn><isbn>0780397827</isbn><isbn>9780780397828</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFjk1LxDAYhOMXuK57F7zkD7S-SZovLyJ1V4XVHqx4XNL2jUS37dIURH-9BRVnYObwwDCEnDFIGQN78VTkecoBVMqNMMbukRPQBoTVhut9MuNMZQnToA7-AbOHf0BpdUwWMb7BpExmAviMXD2Uj8vykt5gDK8ddV1Di90Y2vDlxtB3tPfU0Zcw4BZjpNMDWmIc6WpwLX70w_spOfJuG3Hx23PyvFqW-V2yLm7v8-t1EpiWY1KJ2itfOV5Jpyz3oGXNdMOFRws1n2xr7zhrcEpoEFEaqXD6XDObKSXm5PxnN0xssxtC64bPTQZKgDTiG_v2TEU</recordid><startdate>200609</startdate><enddate>200609</enddate><creator>Dan Zhao</creator><creator>Yi Wang</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200609</creationdate><title>MTNET: Design and Optimization of a Wireless SOC Test Framework</title><author>Dan Zhao ; Yi Wang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-b3cf6fba2b5a692f075c17d23fe90c2c2c9cfa21defa20deee5856e167c194663</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Automatic testing</topic><topic>Communication system control</topic><topic>Costs</topic><topic>Design optimization</topic><topic>Integrated circuit interconnections</topic><topic>Integrated circuit technology</topic><topic>Job shop scheduling</topic><topic>Network-on-a-chip</topic><topic>Radio frequency</topic><topic>Routing</topic><toplevel>online_resources</toplevel><creatorcontrib>Dan Zhao</creatorcontrib><creatorcontrib>Yi Wang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dan Zhao</au><au>Yi Wang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>MTNET: Design and Optimization of a Wireless SOC Test Framework</atitle><btitle>2006 IEEE International SOC Conference</btitle><stitle>SOCC</stitle><date>2006-09</date><risdate>2006</risdate><spage>239</spage><epage>242</epage><pages>239-242</pages><issn>2164-1676</issn><eissn>2164-1706</eissn><isbn>0780397819</isbn><isbn>9780780397811</isbn><eisbn>0780397827</eisbn><eisbn>9780780397828</eisbn><abstract>This paper focuses on a novel self-configurable multihop wireless on-chip micronetwork, namely MTNet, to serve as the test access architecture for testing next generation billion-transistor SoCs. A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Further, a path driven test scheduling algorithm is developed to design and optimize the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of using MTNet for nanoscale SoC testing.</abstract><pub>IEEE</pub><doi>10.1109/SOCC.2006.283889</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2164-1676 |
| ispartof | 2006 IEEE International SOC Conference, 2006, p.239-242 |
| issn | 2164-1676 2164-1706 |
| language | eng |
| recordid | cdi_ieee_primary_4063058 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Automatic testing Communication system control Costs Design optimization Integrated circuit interconnections Integrated circuit technology Job shop scheduling Network-on-a-chip Radio frequency Routing |
| title | MTNET: Design and Optimization of a Wireless SOC Test Framework |
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