Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design

In this paper, we first explore sub-threshold Fin-FET circuits design space, finding their optimal power supply point for minimum energy consumption. We then study soft error vulnerability in sub-threshold region. Our experiments indicate that the energy consumption in sub-threshold region can achie...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Xiaoxia Wu, Feng Wang, Yuan Xie
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders Circuits CMOS technology Delay Dynamic voltage scaling Energy consumption FinFETs Inverters Power supplies Threshold voltage
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