Ka-Band (35 GHz) Low-noise 180 nm SOI CMOS Amplifier

We present the development of a coplanar waveguide (CPW) Ka-band (35 GHz) low-noise amplifier (LNA) designed in MIT-Lincoln Laboratory (MIT-LL) 180 nm fully depleted silicon-on-insulator (FDSOI) CMOS technology fabricated on a "float zone" (2000 ohm-cm) substrate. The LNA exhibits a noise...

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Hauptverfasser: Riemer, P.J., Prairie, J.F., Buhrow, B.R., Chen, C.L., Keast, C.L., Wyatt, P.W., Randall, B.A., Gilbert, B.K., Daniel, E.S.
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creator Riemer, P.J.
Prairie, J.F.
Buhrow, B.R.
Chen, C.L.
Keast, C.L.
Wyatt, P.W.
Randall, B.A.
Gilbert, B.K.
Daniel, E.S.
description We present the development of a coplanar waveguide (CPW) Ka-band (35 GHz) low-noise amplifier (LNA) designed in MIT-Lincoln Laboratory (MIT-LL) 180 nm fully depleted silicon-on-insulator (FDSOI) CMOS technology fabricated on a "float zone" (2000 ohm-cm) substrate. The LNA exhibits a noise figure of 6.5 dB and an associated gain of 6.7 dB at 37 GHz while consuming 27.5 mW of DC power. When biased for maximum gain the LNA exhibits 7.3 dB gain at 35.8 GHz
doi_str_mv 10.1109/SOI.2006.284467
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subjects CMOS technology
Coplanar waveguides
Fabrication
Gain
Laboratories
Low-noise amplifiers
MMICs
Noise figure
Power transmission lines
title Ka-Band (35 GHz) Low-noise 180 nm SOI CMOS Amplifier
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