Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors

We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D ge...

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Bibliographische Detailangaben

Hauptverfasser:	Xiang-Zheng Bo, Grudowski, P., Adams, V., Loiko, K., Tekleab, D., Filipiak, S., Hackenberg, J., Kolagunta, V., Foisy, M., Li-Te Lin, Fung, K.H., Chi-Hsi Wu, Hsiao-Chin Tuan, Cheek, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Added delay Compressive stress Etching Geometry MOS devices Performance gain Ring oscillators Solid modeling Tensile stress
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