Design of a processor bus interface ASIC for the stream memory controller

The Stream Memory Controller (SMC) is an experimental memory interface which allows hardware-assisted memory access reordering for vector computations in order to maximize the efficiency of the system memory bus. This paper describes the design and test strategies for the SMC Processor Bus Interface...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	McGee, S.W., Klenke, R.H., Aylor, J.H., Schwab, A.J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application specific integrated circuits Circuit testing Computer interfaces Control systems Integrated circuit synthesis Logic design Logic testing Process design Random access memory Sliding mode control
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