A Single-Stream Pipelined Instruction Decompression System for Embedded Microprocessors

For instruction decompression, techniques such as single buffering, double buffering and pipelining have been proposed. However, due to jumping penalty, these techniques incur more delays in pipeline or system has to be stopped to refill the cache buffers. A Pipeline with Back-up for Flushing (PBF)...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Jeang, Yuan-long, Wey, Tzuu-shaang, Wang, Hung-yu, Tai, Chih-chung
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Chip scale packaging Circuits Costs Delay Energy consumption Hardware Microprocessors Pipeline processing Read only memory Reduced instruction set computing
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