A Single-Stream Pipelined Instruction Decompression System for Embedded Microprocessors
For instruction decompression, techniques such as single buffering, double buffering and pipelining have been proposed. However, due to jumping penalty, these techniques incur more delays in pipeline or system has to be stopped to refill the cache buffers. A Pipeline with Back-up for Flushing (PBF)...
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| creator | Jeang, Yuan-long Wey, Tzuu-shaang Wang, Hung-yu Tai, Chih-chung |
| description | For instruction decompression, techniques such as single buffering, double buffering and pipelining have been proposed. However, due to jumping penalty, these techniques incur more delays in pipeline or system has to be stopped to refill the cache buffers. A Pipeline with Back-up for Flushing (PBF) technique has been developed that incurs no delay and without stopping due to jumping. However, the first instruction of each basic block should not be compressed and be put in another ROM, and thus the compression ratio should be sacrificed. This paper improves the PBF technique such that a single program ROM needed only. The simulation results for several benchmarks show that the average compression ratio is decreased about 11%, and the hardware cost deceased about 8%. |
| doi_str_mv | 10.1109/IIH-MSP.2006.265067 |
| format | Conference Proceeding |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Chip scale packaging Circuits Costs Delay Energy consumption Hardware Microprocessors Pipeline processing Read only memory Reduced instruction set computing |
| title | A Single-Stream Pipelined Instruction Decompression System for Embedded Microprocessors |
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