A 65-nm Dual-Core Multithreaded Xeon®Processor With 16-MB L3 Cache

This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm 2 die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2007-01, Vol.42 (1), p.17-25
Hauptverfasser:	Rusu, S., Tam, S., Muljono, H., Ayers, D., Chang, J., Cherkauer, B., Stinson, J., Benoit, J., Varada, R., Leung, J., Limaye, R.D., Vora, S.
Format:	Artikel
Sprache:	eng
Schlagworte:	65-nm process technology Circuit design clock distribution Clocks Computer architecture Frequency leakage reduction Logic microprocessor Microprocessors shared on-die cache Subthreshold current Transistors Voltage voltage domains
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