An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch

This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch comparator. Two analytical models are presented and compared with HSpice simulations. Our results indicate that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of...

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Veröffentlicht in:	IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2006-12, Vol.53 (12), p.1398-1402
Hauptverfasser:	Nikoozadeh, A., Murmann, B.
Format:	Artikel
Sprache:	eng
Schlagworte:	Analytical models Capacitance Capacitor mismatch Capacitors Circuits CMOS Comparators Computer simulation dynamic offset Inverters latch Latches Mathematical analysis MOS devices MOSFET circuits Offsets Switches Switching circuits Threshold voltage
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