Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor

As today's process technologies are combined with steadily increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities in combination with the smaller feature sizes requires that we...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Wichlund, S., Berntsen, F., Aas, E.J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automatic test pattern generation Bandwidth Built-in self-test Circuit faults Circuit testing Costs Delay Design for testability Logic testing Semiconductor device testing
Online-Zugang:	Volltext bestellen
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