Search-Space Optimizations for High-Level ATPG
The mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, the auth...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 89 |
|---|---|
| container_issue | |
| container_start_page | 84 |
| container_title | |
| container_volume | |
| creator | Campos, J. Hussain Al-Asaad |
| description | The mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, the authors need to reduce the search space in the analysis process as early as possible. In this paper, the authors present some optimizations in the search space that speed up the overall test generation process |
| doi_str_mv | 10.1109/MTV.2005.23 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4022233</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4022233</ieee_id><sourcerecordid>4022233</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-a6446f76461b0ae1ce79aa5583069ef0cc0ea9a3ad9f66afb56457196b9b41e93</originalsourceid><addsrcrecordid>eNotj01Lw0AQQBc_wFh78uglf2Dj7MfMusdStBUiFRq9lkmc2JXWhiQI-ust6Lu824On1LWBwhiIt0_Va2EBsLDuRGXWOauRgj9VlxAooiUb6ExlBhG0h-gu1HQYPuCIi4jGZapYC_fNVq87biRfdWPapx8e0-FzyNtDny_T-1aX8iW7fFY9L67Uecu7Qab_nqiXh_tqvtTlavE4n5U6mYCjZvKe2kCeTA0sppEQmRHvHFCUFpoGhCM7fostEbc1ksdgItWx9kaim6ibv24SkU3Xpz333xsP1h4n3S8fSUKd</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Search-Space Optimizations for High-Level ATPG</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Campos, J. ; Hussain Al-Asaad</creator><creatorcontrib>Campos, J. ; Hussain Al-Asaad</creatorcontrib><description>The mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, the authors need to reduce the search space in the analysis process as early as possible. In this paper, the authors present some optimizations in the search space that speed up the overall test generation process</description><identifier>ISSN: 1550-4093</identifier><identifier>ISBN: 0769526276</identifier><identifier>ISBN: 9780769526270</identifier><identifier>EISSN: 2332-5674</identifier><identifier>DOI: 10.1109/MTV.2005.23</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automatic test pattern generation ; Boolean functions ; Computational modeling ; Computer simulation ; Data mining ; Debugging ; Logic testing ; Microprocessors ; Sequential analysis ; Test pattern generators</subject><ispartof>2005 Sixth International Workshop on Microprocessor Test and Verification, 2005, p.84-89</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4022233$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4022233$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Campos, J.</creatorcontrib><creatorcontrib>Hussain Al-Asaad</creatorcontrib><title>Search-Space Optimizations for High-Level ATPG</title><title>2005 Sixth International Workshop on Microprocessor Test and Verification</title><addtitle>MTV</addtitle><description>The mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, the authors need to reduce the search space in the analysis process as early as possible. In this paper, the authors present some optimizations in the search space that speed up the overall test generation process</description><subject>Automatic test pattern generation</subject><subject>Boolean functions</subject><subject>Computational modeling</subject><subject>Computer simulation</subject><subject>Data mining</subject><subject>Debugging</subject><subject>Logic testing</subject><subject>Microprocessors</subject><subject>Sequential analysis</subject><subject>Test pattern generators</subject><issn>1550-4093</issn><issn>2332-5674</issn><isbn>0769526276</isbn><isbn>9780769526270</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj01Lw0AQQBc_wFh78uglf2Dj7MfMusdStBUiFRq9lkmc2JXWhiQI-ust6Lu824On1LWBwhiIt0_Va2EBsLDuRGXWOauRgj9VlxAooiUb6ExlBhG0h-gu1HQYPuCIi4jGZapYC_fNVq87biRfdWPapx8e0-FzyNtDny_T-1aX8iW7fFY9L67Uecu7Qab_nqiXh_tqvtTlavE4n5U6mYCjZvKe2kCeTA0sppEQmRHvHFCUFpoGhCM7fostEbc1ksdgItWx9kaim6ibv24SkU3Xpz333xsP1h4n3S8fSUKd</recordid><startdate>200511</startdate><enddate>200511</enddate><creator>Campos, J.</creator><creator>Hussain Al-Asaad</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200511</creationdate><title>Search-Space Optimizations for High-Level ATPG</title><author>Campos, J. ; Hussain Al-Asaad</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-a6446f76461b0ae1ce79aa5583069ef0cc0ea9a3ad9f66afb56457196b9b41e93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Automatic test pattern generation</topic><topic>Boolean functions</topic><topic>Computational modeling</topic><topic>Computer simulation</topic><topic>Data mining</topic><topic>Debugging</topic><topic>Logic testing</topic><topic>Microprocessors</topic><topic>Sequential analysis</topic><topic>Test pattern generators</topic><toplevel>online_resources</toplevel><creatorcontrib>Campos, J.</creatorcontrib><creatorcontrib>Hussain Al-Asaad</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Campos, J.</au><au>Hussain Al-Asaad</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Search-Space Optimizations for High-Level ATPG</atitle><btitle>2005 Sixth International Workshop on Microprocessor Test and Verification</btitle><stitle>MTV</stitle><date>2005-11</date><risdate>2005</risdate><spage>84</spage><epage>89</epage><pages>84-89</pages><issn>1550-4093</issn><eissn>2332-5674</eissn><isbn>0769526276</isbn><isbn>9780769526270</isbn><abstract>The mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, the authors need to reduce the search space in the analysis process as early as possible. In this paper, the authors present some optimizations in the search space that speed up the overall test generation process</abstract><pub>IEEE</pub><doi>10.1109/MTV.2005.23</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1550-4093 |
| ispartof | 2005 Sixth International Workshop on Microprocessor Test and Verification, 2005, p.84-89 |
| issn | 1550-4093 2332-5674 |
| language | eng |
| recordid | cdi_ieee_primary_4022233 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Automatic test pattern generation Boolean functions Computational modeling Computer simulation Data mining Debugging Logic testing Microprocessors Sequential analysis Test pattern generators |
| title | Search-Space Optimizations for High-Level ATPG |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T07%3A53%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Search-Space%20Optimizations%20for%20High-Level%20ATPG&rft.btitle=2005%20Sixth%20International%20Workshop%20on%20Microprocessor%20Test%20and%20Verification&rft.au=Campos,%20J.&rft.date=2005-11&rft.spage=84&rft.epage=89&rft.pages=84-89&rft.issn=1550-4093&rft.eissn=2332-5674&rft.isbn=0769526276&rft.isbn_list=9780769526270&rft_id=info:doi/10.1109/MTV.2005.23&rft_dat=%3Cieee_6IE%3E4022233%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4022233&rfr_iscdi=true |