A Synthesis Technique for Reducing Leakage Based on Signal Controllability

Leakage is becoming a dominant factor in the total power consumption of a logic circuit. Most of the methods presented in the literature are based on adding a sleep input to the circuit that allow an external controller to turn the circuit off when it is not switching. Limited work has been done in...

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Bibliographische Detailangaben

Hauptverfasser:	Elkarablieh, B., Nunez-Aldana, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit synthesis CMOS technology Controllability Energy consumption Leakage Reduction Libraries Logic circuits Signal Controllability Signal Probability Signal synthesis Sleep Switching circuits Timing
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