Millisecond Anneal and Short-Channel Effect Control in Si CMOS Transistor Performance
In this letter, the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices are studied. The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation....
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| Veröffentlicht in: | IEEE electron device letters 2006-12, Vol.27 (12), p.969-971 |
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| container_end_page | 971 |
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| container_issue | 12 |
| container_start_page | 969 |
| container_title | IEEE electron device letters |
| container_volume | 27 |
| creator | Nieh, C.F. Ku, K.C. Chen, C.H. Chang, H. Wang, L.T. Huang, L.P. Sheu, Y.M. Wang, C.C. Lee, T.L. Chen, S.C. Liang, M.S. Gong, J. |
| description | In this letter, the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices are studied. The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation. On blanket Si wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short-channel effect behaviors in the fabricated CMOS devices, resulting in opposite threshold-voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. The results also provide useful insights into ultrashallow-junction formation and short-channel effect control when scaling CMOS technology |
| doi_str_mv | 10.1109/LED.2006.886317 |
| format | Article |
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The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation. On blanket Si wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short-channel effect behaviors in the fabricated CMOS devices, resulting in opposite threshold-voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. The results also provide useful insights into ultrashallow-junction formation and short-channel effect control when scaling CMOS technology</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2006.886317</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Annealing ; Applied sciences ; Boron ; CMOS ; CMOS technology ; Compound structure devices ; Crystal structure ; Design. Technologies. Operation analysis. Testing ; Devices ; Electronics ; Exact sciences and technology ; Fabrication ; Implants ; Integrated circuits ; MOS devices ; P-n junctions ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; short-channel effect (SCE) ; Silicon ; Solids ; Spikes ; Temperature ; Transistors ; ultrashallow junction (USJ)</subject><ispartof>IEEE electron device letters, 2006-12, Vol.27 (12), p.969-971</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation. On blanket Si wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short-channel effect behaviors in the fabricated CMOS devices, resulting in opposite threshold-voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. The results also provide useful insights into ultrashallow-junction formation and short-channel effect control when scaling CMOS technology</description><subject>Annealing</subject><subject>Applied sciences</subject><subject>Boron</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Compound structure devices</subject><subject>Crystal structure</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Devices</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Fabrication</subject><subject>Implants</subject><subject>Integrated circuits</subject><subject>MOS devices</subject><subject>P-n junctions</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>short-channel effect (SCE)</subject><subject>Silicon</subject><subject>Solids</subject><subject>Spikes</subject><subject>Temperature</subject><subject>Transistors</subject><subject>ultrashallow junction (USJ)</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkE1rGzEQhkVoIY7bcw-5iECgl3VmVh-rPYat-wEOKTg5C1mRiIIsJdL60H9fBYcGehg0aJ55GR5CviCsEGG82qy_rXoAuVJKMhxOyAKFUB0IyT6QBQwcO4YgT8lZrU8AyPnAF-T-JsQYqrM5PdDrlJyJ1LR2-5jL3E2Ppn1Fuvbe2ZlOOc0lRxoS3QY63dxu6V0xqYY650J_u-Jz2Ztk3Sfy0ZtY3ee3d0nuv6_vpp_d5vbHr-l601nG-rkb_I7tdsKgAjYyFHLojRMgECxnpg0FcGcYd2DsKHr0yu_6kQMYJdzDoNiSfD3mPpf8cnB11vtQrYvRJJcPVaMcsB8Ea_lLcvEf-pQPJbXr9Ig9tJLYoKsjZEuutTivn0vYm_JHI-hXy7pZ1q-W9dFy27h8izXVmuibDhvq-5piHEYpGnd-5IJz7t-YA0ocFfsLEOeC9g</recordid><startdate>200612</startdate><enddate>200612</enddate><creator>Nieh, C.F.</creator><creator>Ku, K.C.</creator><creator>Chen, C.H.</creator><creator>Chang, H.</creator><creator>Wang, L.T.</creator><creator>Huang, L.P.</creator><creator>Sheu, Y.M.</creator><creator>Wang, C.C.</creator><creator>Lee, T.L.</creator><creator>Chen, S.C.</creator><creator>Liang, M.S.</creator><creator>Gong, J.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Technologies. Operation analysis. Testing</topic><topic>Devices</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Fabrication</topic><topic>Implants</topic><topic>Integrated circuits</topic><topic>MOS devices</topic><topic>P-n junctions</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>short-channel effect (SCE)</topic><topic>Silicon</topic><topic>Solids</topic><topic>Spikes</topic><topic>Temperature</topic><topic>Transistors</topic><topic>ultrashallow junction (USJ)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Nieh, C.F.</creatorcontrib><creatorcontrib>Ku, K.C.</creatorcontrib><creatorcontrib>Chen, C.H.</creatorcontrib><creatorcontrib>Chang, H.</creatorcontrib><creatorcontrib>Wang, L.T.</creatorcontrib><creatorcontrib>Huang, L.P.</creatorcontrib><creatorcontrib>Sheu, Y.M.</creatorcontrib><creatorcontrib>Wang, C.C.</creatorcontrib><creatorcontrib>Lee, T.L.</creatorcontrib><creatorcontrib>Chen, S.C.</creatorcontrib><creatorcontrib>Liang, M.S.</creatorcontrib><creatorcontrib>Gong, J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nieh, C.F.</au><au>Ku, K.C.</au><au>Chen, C.H.</au><au>Chang, H.</au><au>Wang, L.T.</au><au>Huang, L.P.</au><au>Sheu, Y.M.</au><au>Wang, C.C.</au><au>Lee, T.L.</au><au>Chen, S.C.</au><au>Liang, M.S.</au><au>Gong, J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Millisecond Anneal and Short-Channel Effect Control in Si CMOS Transistor Performance</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2006-12</date><risdate>2006</risdate><volume>27</volume><issue>12</issue><spage>969</spage><epage>971</epage><pages>969-971</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>In this letter, the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices are studied. The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation. On blanket Si wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short-channel effect behaviors in the fabricated CMOS devices, resulting in opposite threshold-voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. The results also provide useful insights into ultrashallow-junction formation and short-channel effect control when scaling CMOS technology</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/LED.2006.886317</doi><tpages>3</tpages></addata></record> |
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| subjects | Annealing Applied sciences Boron CMOS CMOS technology Compound structure devices Crystal structure Design. Technologies. Operation analysis. Testing Devices Electronics Exact sciences and technology Fabrication Implants Integrated circuits MOS devices P-n junctions Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices short-channel effect (SCE) Silicon Solids Spikes Temperature Transistors ultrashallow junction (USJ) |
| title | Millisecond Anneal and Short-Channel Effect Control in Si CMOS Transistor Performance |
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