A fault tolerant system configuration based on error correcting codes

A fault tolerant system configuration composed of multiple computers is discussed. We propose a new error correction procedure based on the theory of error correcting codes and information theory. We assume that the system is composed of J computers, and each computer, N modules, where the word-leng...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Hirasawa, S., Kohnosu, T., Nishijima, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 2475 vol.3
container_issue
container_start_page 2470
container_title
container_volume 3
creator Hirasawa, S.
Kohnosu, T.
Nishijima, T.
description A fault tolerant system configuration composed of multiple computers is discussed. We propose a new error correction procedure based on the theory of error correcting codes and information theory. We assume that the system is composed of J computers, and each computer, N modules, where the word-length of the computer is w bits. Each module has a m bits memory and w bits CPU. We also assume that each computer is loosely coupled to the other computers, while each module is tightly coupled to the other modules in each computer. Then we introduce an (N, K) code over GF(2/sup m/) in each computer, where w=mK. The proposed system is able to construct a (JN, K) code over GF(2/sup m/) by combining J computers which consist of JN modules. If at least one computer detects errors, then the (JN, K) code is decoded to correct errors. Thus the proposed system can increase the error correcting capability and errors which result in only detecting errors or decoding errors for the conventional system can be corrected, where the conventional system is assumed to be the L out of J system. Comparing the proposed system with the conventional system, we show that the performance of the former is superior than that of the latter.< >
doi_str_mv 10.1109/ICSMC.1994.400238
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_400238</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>400238</ieee_id><sourcerecordid>400238</sourcerecordid><originalsourceid>FETCH-LOGICAL-i104t-4a996bf00c16f1ebb0b77bbb69ca54e070b877d9aa425653abef46b6b9b1ecc23</originalsourceid><addsrcrecordid>eNotj8FqwzAQRAWl0JL6A9KTfsDuypYl6xhM2gZSemhzDlp5FVQcu0jKIX9fQzoMzIOBgWFsLaASAszLrv_66CthjKwkQN10d6wwuoPFTS1q0z2wIqUfWCTbVgr9yLYb7u1lzDzPI0U7ZZ6uKdOZu3ny4XSJNod54mgTDXwBinGOSxkjuRym04IDpSd27-2YqPjPFTu8br_793L_-bbrN_syCJC5lNYYhR7ACeUFIQJqjYjKONtKAg3YaT0Ya2XdqraxSF4qVGhQkHN1s2LPt91ARMffGM42Xo-3r80fcX9LNg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A fault tolerant system configuration based on error correcting codes</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Hirasawa, S. ; Kohnosu, T. ; Nishijima, T.</creator><creatorcontrib>Hirasawa, S. ; Kohnosu, T. ; Nishijima, T.</creatorcontrib><description>A fault tolerant system configuration composed of multiple computers is discussed. We propose a new error correction procedure based on the theory of error correcting codes and information theory. We assume that the system is composed of J computers, and each computer, N modules, where the word-length of the computer is w bits. Each module has a m bits memory and w bits CPU. We also assume that each computer is loosely coupled to the other computers, while each module is tightly coupled to the other modules in each computer. Then we introduce an (N, K) code over GF(2/sup m/) in each computer, where w=mK. The proposed system is able to construct a (JN, K) code over GF(2/sup m/) by combining J computers which consist of JN modules. If at least one computer detects errors, then the (JN, K) code is decoded to correct errors. Thus the proposed system can increase the error correcting capability and errors which result in only detecting errors or decoding errors for the conventional system can be corrected, where the conventional system is assumed to be the L out of J system. Comparing the proposed system with the conventional system, we show that the performance of the former is superior than that of the latter.&lt; &gt;</description><identifier>ISBN: 9780780321298</identifier><identifier>ISBN: 0780321294</identifier><identifier>DOI: 10.1109/ICSMC.1994.400238</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer errors ; Concurrent computing ; Decoding ; Engineering management ; Error correction ; Error correction codes ; Fault tolerant systems ; IEEE members ; Industrial engineering ; Telecommunication computing</subject><ispartof>Proceedings of IEEE International Conference on Systems, Man and Cybernetics, 1994, Vol.3, p.2470-2475 vol.3</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/400238$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/400238$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hirasawa, S.</creatorcontrib><creatorcontrib>Kohnosu, T.</creatorcontrib><creatorcontrib>Nishijima, T.</creatorcontrib><title>A fault tolerant system configuration based on error correcting codes</title><title>Proceedings of IEEE International Conference on Systems, Man and Cybernetics</title><addtitle>ICSMC</addtitle><description>A fault tolerant system configuration composed of multiple computers is discussed. We propose a new error correction procedure based on the theory of error correcting codes and information theory. We assume that the system is composed of J computers, and each computer, N modules, where the word-length of the computer is w bits. Each module has a m bits memory and w bits CPU. We also assume that each computer is loosely coupled to the other computers, while each module is tightly coupled to the other modules in each computer. Then we introduce an (N, K) code over GF(2/sup m/) in each computer, where w=mK. The proposed system is able to construct a (JN, K) code over GF(2/sup m/) by combining J computers which consist of JN modules. If at least one computer detects errors, then the (JN, K) code is decoded to correct errors. Thus the proposed system can increase the error correcting capability and errors which result in only detecting errors or decoding errors for the conventional system can be corrected, where the conventional system is assumed to be the L out of J system. Comparing the proposed system with the conventional system, we show that the performance of the former is superior than that of the latter.&lt; &gt;</description><subject>Computer errors</subject><subject>Concurrent computing</subject><subject>Decoding</subject><subject>Engineering management</subject><subject>Error correction</subject><subject>Error correction codes</subject><subject>Fault tolerant systems</subject><subject>IEEE members</subject><subject>Industrial engineering</subject><subject>Telecommunication computing</subject><isbn>9780780321298</isbn><isbn>0780321294</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1994</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8FqwzAQRAWl0JL6A9KTfsDuypYl6xhM2gZSemhzDlp5FVQcu0jKIX9fQzoMzIOBgWFsLaASAszLrv_66CthjKwkQN10d6wwuoPFTS1q0z2wIqUfWCTbVgr9yLYb7u1lzDzPI0U7ZZ6uKdOZu3ny4XSJNod54mgTDXwBinGOSxkjuRym04IDpSd27-2YqPjPFTu8br_793L_-bbrN_syCJC5lNYYhR7ACeUFIQJqjYjKONtKAg3YaT0Ya2XdqraxSF4qVGhQkHN1s2LPt91ARMffGM42Xo-3r80fcX9LNg</recordid><startdate>1994</startdate><enddate>1994</enddate><creator>Hirasawa, S.</creator><creator>Kohnosu, T.</creator><creator>Nishijima, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1994</creationdate><title>A fault tolerant system configuration based on error correcting codes</title><author>Hirasawa, S. ; Kohnosu, T. ; Nishijima, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-4a996bf00c16f1ebb0b77bbb69ca54e070b877d9aa425653abef46b6b9b1ecc23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1994</creationdate><topic>Computer errors</topic><topic>Concurrent computing</topic><topic>Decoding</topic><topic>Engineering management</topic><topic>Error correction</topic><topic>Error correction codes</topic><topic>Fault tolerant systems</topic><topic>IEEE members</topic><topic>Industrial engineering</topic><topic>Telecommunication computing</topic><toplevel>online_resources</toplevel><creatorcontrib>Hirasawa, S.</creatorcontrib><creatorcontrib>Kohnosu, T.</creatorcontrib><creatorcontrib>Nishijima, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hirasawa, S.</au><au>Kohnosu, T.</au><au>Nishijima, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A fault tolerant system configuration based on error correcting codes</atitle><btitle>Proceedings of IEEE International Conference on Systems, Man and Cybernetics</btitle><stitle>ICSMC</stitle><date>1994</date><risdate>1994</risdate><volume>3</volume><spage>2470</spage><epage>2475 vol.3</epage><pages>2470-2475 vol.3</pages><isbn>9780780321298</isbn><isbn>0780321294</isbn><abstract>A fault tolerant system configuration composed of multiple computers is discussed. We propose a new error correction procedure based on the theory of error correcting codes and information theory. We assume that the system is composed of J computers, and each computer, N modules, where the word-length of the computer is w bits. Each module has a m bits memory and w bits CPU. We also assume that each computer is loosely coupled to the other computers, while each module is tightly coupled to the other modules in each computer. Then we introduce an (N, K) code over GF(2/sup m/) in each computer, where w=mK. The proposed system is able to construct a (JN, K) code over GF(2/sup m/) by combining J computers which consist of JN modules. If at least one computer detects errors, then the (JN, K) code is decoded to correct errors. Thus the proposed system can increase the error correcting capability and errors which result in only detecting errors or decoding errors for the conventional system can be corrected, where the conventional system is assumed to be the L out of J system. Comparing the proposed system with the conventional system, we show that the performance of the former is superior than that of the latter.&lt; &gt;</abstract><pub>IEEE</pub><doi>10.1109/ICSMC.1994.400238</doi></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 9780780321298
ispartof Proceedings of IEEE International Conference on Systems, Man and Cybernetics, 1994, Vol.3, p.2470-2475 vol.3
issn
language eng
recordid cdi_ieee_primary_400238
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Computer errors
Concurrent computing
Decoding
Engineering management
Error correction
Error correction codes
Fault tolerant systems
IEEE members
Industrial engineering
Telecommunication computing
title A fault tolerant system configuration based on error correcting codes
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T15%3A01%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20fault%20tolerant%20system%20configuration%20based%20on%20error%20correcting%20codes&rft.btitle=Proceedings%20of%20IEEE%20International%20Conference%20on%20Systems,%20Man%20and%20Cybernetics&rft.au=Hirasawa,%20S.&rft.date=1994&rft.volume=3&rft.spage=2470&rft.epage=2475%20vol.3&rft.pages=2470-2475%20vol.3&rft.isbn=9780780321298&rft.isbn_list=0780321294&rft_id=info:doi/10.1109/ICSMC.1994.400238&rft_dat=%3Cieee_6IE%3E400238%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=400238&rfr_iscdi=true