A VHDL synthesis approach to the IEEE P1149.5 bus standard

This paper describes an implementation strategy for the emerging IEEE standard, P1149.5 (Standard Module Test and Maintenance Bus). The approach uses the VHSIC Hardware Description Language (VHDL) to perform a top down design from the behavioral level to a synthesizable level. From the synthesizable...

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1. Verfasser:	Kerr, J.L.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Built-in self-test Clocks Costs Electronic equipment testing Instruments Libraries Master-slave Performance evaluation System testing Wire
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creator	Kerr, J.L.
description	This paper describes an implementation strategy for the emerging IEEE standard, P1149.5 (Standard Module Test and Maintenance Bus). The approach uses the VHSIC Hardware Description Language (VHDL) to perform a top down design from the behavioral level to a synthesizable level. From the synthesizable level, a gate level VHDL netlist can be generated. A library of synthesizable VHDL modules allows various levels of user customization. By using standard building blocks, designers can concentrate on their specific P1149.5 interface requirements rather than the details of the required functions of P1149.5.< >
doi_str_mv	10.1109/AUTEST.1993.396358
format	Conference Proceeding
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subjects	Built-in self-test Clocks Costs Electronic equipment testing Instruments Libraries Master-slave Performance evaluation System testing Wire
title	A VHDL synthesis approach to the IEEE P1149.5 bus standard
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