Pixel processing in a memory controller
The SX-a programmable pixel processor implemented in a workstation memory controller chip-aims to perform as well as low-end 2D and 3D graphics processors and to surpass low-end imaging accelerators. The following features help accomplish this goal: large internal register set; vectorized RISC-like...
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| Veröffentlicht in: | IEEE computer graphics and applications 1995-01, Vol.15 (1), p.51-61 |
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| container_end_page | 61 |
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| container_issue | 1 |
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| container_title | IEEE computer graphics and applications |
| container_volume | 15 |
| creator | Donovan, W. Sabella, P. Kabir, I. Hsieh, M.M. |
| description | The SX-a programmable pixel processor implemented in a workstation memory controller chip-aims to perform as well as low-end 2D and 3D graphics processors and to surpass low-end imaging accelerators. The following features help accomplish this goal: large internal register set; vectorized RISC-like instruction set; fast access to both main and video memory; fast pixel operations; free operations; unpolluted cache; and single-chip solution. We describe the workstation configuration we used for our tests and the SX processor architecture, followed by the SX instruction set and sample algorithms. Then we present SX performance results for a wide range of operations.< > |
| doi_str_mv | 10.1109/38.364964 |
| format | Magazinearticle |
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| ispartof | IEEE computer graphics and applications, 1995-01, Vol.15 (1), p.51-61 |
| issn | 0272-1716 1558-1756 |
| language | eng |
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| source | IEEE Xplore |
| subjects | Applied sciences Artificial intelligence Clocks Computer science control theory systems Computer systems and distributed systems. User interface Costs Displays Exact sciences and technology Graphics Image processing Pattern recognition. Digital image processing. Computational geometry Pixel Random access memory Registers Rendering (computer graphics) Software Workstations |
| title | Pixel processing in a memory controller |
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