Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

The long-term reliability for a p/sup +/ poly gate MOS structure under low electric field bias temperature (BT) stress is studied. A significant increase in interface-state density was observed for such a structure under positive bias conditions. This phenomenon was not observed in the n/sup +/ poly...

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Veröffentlicht in:	IEEE transactions on electron devices 1989-09, Vol.36 (9), p.1732-1739
Hauptverfasser:	Hiruta, Y., Iwai, H., Matsuoka, F., Hama, K., Maeguchi, K., Kanzaki, K.
Format:	Artikel
Sprache:	eng
Schlagworte:	Boron Electrodes Interface states MOS capacitors MOSFET circuits Semiconductor films Stress Temperature Testing Ultra large scale integration
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