A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM
This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivi...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1994-12, Vol.29 (12), p.1491-1496 |
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| container_end_page | 1496 |
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| container_issue | 12 |
| container_start_page | 1491 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 29 |
| creator | Lee, T.H. Donnelly, K.S. Ho, J.T.C. Zerbe, J. Johnson, M.G. Ishikawa, T. |
| description | This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2/spl pi/ radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface.< > |
| doi_str_mv | 10.1109/4.340422 |
| format | Article |
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Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2/spl pi/ radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.340422</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit noise ; Clocks ; Delay ; DRAM chips ; Electronics ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Jitter ; Phase locked loops ; Random access memory ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Voltage control ; Voltage-controlled oscillators ; Working environment noise</subject><ispartof>IEEE journal of solid-state circuits, 1994-12, Vol.29 (12), p.1491-1496</ispartof><rights>1995 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c304t-8b43a4d5f9af4252d3544676666bb77bb73bd3c645f4d888a88501bfad1c3e3a3</citedby><cites>FETCH-LOGICAL-c304t-8b43a4d5f9af4252d3544676666bb77bb73bd3c645f4d888a88501bfad1c3e3a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/340422$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,796,23930,23931,25140,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/340422$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=3365135$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Lee, T.H.</creatorcontrib><creatorcontrib>Donnelly, K.S.</creatorcontrib><creatorcontrib>Ho, J.T.C.</creatorcontrib><creatorcontrib>Zerbe, J.</creatorcontrib><creatorcontrib>Johnson, M.G.</creatorcontrib><creatorcontrib>Ishikawa, T.</creatorcontrib><title>A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2/spl pi/ radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface.< ></description><subject>Applied sciences</subject><subject>Circuit noise</subject><subject>Clocks</subject><subject>Delay</subject><subject>DRAM chips</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Jitter</subject><subject>Phase locked loops</subject><subject>Random access memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Voltage control</subject><subject>Voltage-controlled oscillators</subject><subject>Working environment noise</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1994</creationdate><recordtype>article</recordtype><recordid>eNpFkEtLAzEURoMoWKvg2lUWIi6cNs-ZdCVlfEJLwRfuQp4ymjY1mS767x2Zohcul497OIsPgFOMRhijyZiNKEOMkD0wwJyLAlf0fR8MEMKimBCEDsFRzp9dZEzgAbieQjLi8A3W88UztC6obRGi-XIWhhjX0McEsYBz3bRXkCMEl-5D6W3rxhnePE3nx-DAq5Ddye4Owevd7Uv9UMwW94_1dFYYilhbCM2oYpb7ifKMcGIpZ6ysym60rqpuqbbUlIx7ZoUQSgiOsPbKYkMdVXQILnrvOsXvjcutXDbZuBDUysVNlkTgiqASdeBlD5oUc07Oy3VqliptJUbytyHJZN9Qh57vnCobFXxSK9PkP57SkmPKO-ysxxrn3P-3d_wAYBBoAw</recordid><startdate>19941201</startdate><enddate>19941201</enddate><creator>Lee, T.H.</creator><creator>Donnelly, K.S.</creator><creator>Ho, J.T.C.</creator><creator>Zerbe, J.</creator><creator>Johnson, M.G.</creator><creator>Ishikawa, T.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19941201</creationdate><title>A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM</title><author>Lee, T.H. ; Donnelly, K.S. ; Ho, J.T.C. ; Zerbe, J. ; Johnson, M.G. ; Ishikawa, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c304t-8b43a4d5f9af4252d3544676666bb77bb73bd3c645f4d888a88501bfad1c3e3a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1994</creationdate><topic>Applied sciences</topic><topic>Circuit noise</topic><topic>Clocks</topic><topic>Delay</topic><topic>DRAM chips</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Jitter</topic><topic>Phase locked loops</topic><topic>Random access memory</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Voltage control</topic><topic>Voltage-controlled oscillators</topic><topic>Working environment noise</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lee, T.H.</creatorcontrib><creatorcontrib>Donnelly, K.S.</creatorcontrib><creatorcontrib>Ho, J.T.C.</creatorcontrib><creatorcontrib>Zerbe, J.</creatorcontrib><creatorcontrib>Johnson, M.G.</creatorcontrib><creatorcontrib>Ishikawa, T.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, T.H.</au><au>Donnelly, K.S.</au><au>Ho, J.T.C.</au><au>Zerbe, J.</au><au>Johnson, M.G.</au><au>Ishikawa, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1994-12-01</date><risdate>1994</risdate><volume>29</volume><issue>12</issue><spage>1491</spage><epage>1496</epage><pages>1491-1496</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2/spl pi/ radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.340422</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1994-12, Vol.29 (12), p.1491-1496 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_340422 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit noise Clocks Delay DRAM chips Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Jitter Phase locked loops Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Voltage control Voltage-controlled oscillators Working environment noise |
| title | A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM |
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