Short destabilizing paths in timing verification
Designing an optimal clocking scheme for a sequential circuit requires accurate knowledge of the delay of its longest sensitizable and of its shortest destabilizing path. However, there is a large imbalance in the research effort spent on both types of paths. This paper tries to compensate this imba...
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| creator | Llopis, R.P. Xirgo, L.R. Bordoll, J.C. |
| description | Designing an optimal clocking scheme for a sequential circuit requires accurate knowledge of the delay of its longest sensitizable and of its shortest destabilizing path. However, there is a large imbalance in the research effort spent on both types of paths. This paper tries to compensate this imbalance, by presenting a new destabilizing criterion, for which it will be proved that it leads to correct optimal clocking schemes. Furthermore, this paper results in clocking schemes which are tighter in comparison with those presented in literature.< > |
| doi_str_mv | 10.1109/ICCD.1994.331879 |
| format | Conference Proceeding |
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However, there is a large imbalance in the research effort spent on both types of paths. This paper tries to compensate this imbalance, by presenting a new destabilizing criterion, for which it will be proved that it leads to correct optimal clocking schemes. Furthermore, this paper results in clocking schemes which are tighter in comparison with those presented in literature.< ></description><identifier>ISBN: 9780818665653</identifier><identifier>ISBN: 0818665653</identifier><identifier>DOI: 10.1109/ICCD.1994.331879</identifier><language>eng</language><publisher>IEEE Comput. Soc. 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Furthermore, this paper results in clocking schemes which are tighter in comparison with those presented in literature.< ></description><subject>Clocks</subject><subject>Delay effects</subject><subject>Delay estimation</subject><subject>Digital systems</subject><subject>Feedback</subject><subject>Feeds</subject><subject>Latches</subject><subject>Propagation delay</subject><subject>Sequential circuits</subject><subject>Timing</subject><isbn>9780818665653</isbn><isbn>0818665653</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1994</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0tLAzEURgMiKHX24mr-wIw372Qp46tQcKGuSzK5sVfaaZkEQX-9SvttDmdz4GPsmkPPOfjb5TDc99x71UvJnfVnrPHWgePOGG20vGBNKZ_wN60dWHvJ4HWzn2ubsNQQaUs_NH20h1A3paWprbT79y-cKdMYKu2nK3aew7Zgc-KCvT8-vA3P3erlaTncrTrioGrnNIZsAji0IITlOhkVhU9GByV1Fpik80mMMSoZXZKKjyNYTJCy9IhOLtjNsUuIuD7MtAvz9_p4S_4COR1Cww</recordid><startdate>1994</startdate><enddate>1994</enddate><creator>Llopis, R.P.</creator><creator>Xirgo, L.R.</creator><creator>Bordoll, J.C.</creator><general>IEEE Comput. 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However, there is a large imbalance in the research effort spent on both types of paths. This paper tries to compensate this imbalance, by presenting a new destabilizing criterion, for which it will be proved that it leads to correct optimal clocking schemes. Furthermore, this paper results in clocking schemes which are tighter in comparison with those presented in literature.< ></abstract><pub>IEEE Comput. Soc. Press</pub><doi>10.1109/ICCD.1994.331879</doi><tpages>4</tpages></addata></record> |
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| identifier | ISBN: 9780818665653 |
| ispartof | Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994, p.160-163 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Delay effects Delay estimation Digital systems Feedback Feeds Latches Propagation delay Sequential circuits Timing |
| title | Short destabilizing paths in timing verification |
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