How datapath allocation affects controller delay
We present an allocation approach which considers the controller's effect on system delay to minimize the system cycle time. Most allocation algorithms and conditional resource sharing methods emphasize minimum number of resources or area. Previous works have not modeled the resulting controlle...
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| creator | Huang, S.C.-Y. Wolf, W.H. |
| description | We present an allocation approach which considers the controller's effect on system delay to minimize the system cycle time. Most allocation algorithms and conditional resource sharing methods emphasize minimum number of resources or area. Previous works have not modeled the resulting controller's structure and its contribution to the system delay in a controller/datapath system. The allocation method generates a controller with minimum delay on the system's critical path. Therefore the resulting system cycle time will be shorter than other allocation approaches.< > |
| doi_str_mv | 10.1109/ISHLS.1994.302326 |
| format | Conference Proceeding |
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Most allocation algorithms and conditional resource sharing methods emphasize minimum number of resources or area. Previous works have not modeled the resulting controller's structure and its contribution to the system delay in a controller/datapath system. The allocation method generates a controller with minimum delay on the system's critical path. Therefore the resulting system cycle time will be shorter than other allocation approaches.< ></description><identifier>ISBN: 0818657855</identifier><identifier>ISBN: 9780818657856</identifier><identifier>DOI: 10.1109/ISHLS.1994.302326</identifier><language>eng</language><publisher>IEEE Comput. Soc. Press</publisher><subject>Control system synthesis ; Control systems ; Delay effects ; Delay systems ; Flow graphs ; Iterative methods ; Logic ; Registers ; Resource management ; Timing</subject><ispartof>Proceedings of 7th International Symposium on High-Level Synthesis, 1994, p.158-163</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/302326$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/302326$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Huang, S.C.-Y.</creatorcontrib><creatorcontrib>Wolf, W.H.</creatorcontrib><title>How datapath allocation affects controller delay</title><title>Proceedings of 7th International Symposium on High-Level Synthesis</title><addtitle>ISHLS</addtitle><description>We present an allocation approach which considers the controller's effect on system delay to minimize the system cycle time. Most allocation algorithms and conditional resource sharing methods emphasize minimum number of resources or area. Previous works have not modeled the resulting controller's structure and its contribution to the system delay in a controller/datapath system. The allocation method generates a controller with minimum delay on the system's critical path. Therefore the resulting system cycle time will be shorter than other allocation approaches.< ></description><subject>Control system synthesis</subject><subject>Control systems</subject><subject>Delay effects</subject><subject>Delay systems</subject><subject>Flow graphs</subject><subject>Iterative methods</subject><subject>Logic</subject><subject>Registers</subject><subject>Resource management</subject><subject>Timing</subject><isbn>0818657855</isbn><isbn>9780818657856</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1994</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpjYJA0NNAzNDSw1PcM9vAJ1jO0tDTRMzYwMjYyY2bgMrAwtDAzNbcwNeVg4C0uzjIAAhMTEyDJyWDgkV-ukJJYkliQWJKhkJiTk5-cWJKZn6eQmJaWmlxSrJCcn1dSlJ-Tk1qkkJKak1jJw8CalphTnMoLpbkZpNxcQ5w9dDNTU1PjC4oycxOLKuMhdhvjlQQAuMwyyg</recordid><startdate>1994</startdate><enddate>1994</enddate><creator>Huang, S.C.-Y.</creator><creator>Wolf, W.H.</creator><general>IEEE Comput. Soc. Press</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1994</creationdate><title>How datapath allocation affects controller delay</title><author>Huang, S.C.-Y. ; Wolf, W.H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_3023263</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1994</creationdate><topic>Control system synthesis</topic><topic>Control systems</topic><topic>Delay effects</topic><topic>Delay systems</topic><topic>Flow graphs</topic><topic>Iterative methods</topic><topic>Logic</topic><topic>Registers</topic><topic>Resource management</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Huang, S.C.-Y.</creatorcontrib><creatorcontrib>Wolf, W.H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Huang, S.C.-Y.</au><au>Wolf, W.H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>How datapath allocation affects controller delay</atitle><btitle>Proceedings of 7th International Symposium on High-Level Synthesis</btitle><stitle>ISHLS</stitle><date>1994</date><risdate>1994</risdate><spage>158</spage><epage>163</epage><pages>158-163</pages><isbn>0818657855</isbn><isbn>9780818657856</isbn><abstract>We present an allocation approach which considers the controller's effect on system delay to minimize the system cycle time. Most allocation algorithms and conditional resource sharing methods emphasize minimum number of resources or area. Previous works have not modeled the resulting controller's structure and its contribution to the system delay in a controller/datapath system. The allocation method generates a controller with minimum delay on the system's critical path. Therefore the resulting system cycle time will be shorter than other allocation approaches.< ></abstract><pub>IEEE Comput. Soc. Press</pub><doi>10.1109/ISHLS.1994.302326</doi></addata></record> |
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| identifier | ISBN: 0818657855 |
| ispartof | Proceedings of 7th International Symposium on High-Level Synthesis, 1994, p.158-163 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Control system synthesis Control systems Delay effects Delay systems Flow graphs Iterative methods Logic Registers Resource management Timing |
| title | How datapath allocation affects controller delay |
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