Low power design using double edge triggered flip-flops
In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any prev...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 1994-06, Vol.2 (2), p.261-265 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Hossain, R. Wronski, L.D. Albicki, A. |
| description | In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on the effect of input sequences in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity.< > |
| doi_str_mv | 10.1109/92.285754 |
| format | Article |
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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 1994-06, Vol.2 (2), p.261-265 |
| issn | 1063-8210 1557-9999 |
| language | eng |
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| source | IEEE/IET Electronic Library |
| subjects | Analytical models Clocks Digital systems Energy consumption Energy dissipation Flip-flops Frequency Integrated circuit layout Power dissipation Very large scale integration |
| title | Low power design using double edge triggered flip-flops |
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