A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers
A 16-Mb CMOS SRAM using 0.4-/spl mu/m CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1994-04, Vol.29 (4), p.411-418 |
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| container_end_page | 418 |
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| container_issue | 4 |
| container_start_page | 411 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 29 |
| creator | Ishibashi, K. Komiyaji, K. Morita, S. Aoto, T. Ikeda, S. Asayama, K. Koike, A. Yamanaka, T. Hashimoto, N. Iida, H. Kojima, F. Motohashi, K. Sasaki, K. |
| description | A 16-Mb CMOS SRAM using 0.4-/spl mu/m CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm/sup 2/ is fabricated and an address access time of 12.5 ns has been achieved.< > |
| doi_str_mv | 10.1109/4.280689 |
| format | Article |
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This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm/sup 2/ is fabricated and an address access time of 12.5 ns has been achieved.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.280689</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Cache memory ; Capacitors ; Circuit simulation ; CMOS technology ; Costs ; Delay effects ; Random access memory ; Redundancy ; Supercomputers ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 1994-04, Vol.29 (4), p.411-418</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c304t-cd96d8d1fcdd256a0e75ec0174b6001dcc0417ab60c7e8d322e5f2be0ff3657c3</citedby><cites>FETCH-LOGICAL-c304t-cd96d8d1fcdd256a0e75ec0174b6001dcc0417ab60c7e8d322e5f2be0ff3657c3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/280689$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/280689$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ishibashi, K.</creatorcontrib><creatorcontrib>Komiyaji, K.</creatorcontrib><creatorcontrib>Morita, S.</creatorcontrib><creatorcontrib>Aoto, T.</creatorcontrib><creatorcontrib>Ikeda, S.</creatorcontrib><creatorcontrib>Asayama, K.</creatorcontrib><creatorcontrib>Koike, A.</creatorcontrib><creatorcontrib>Yamanaka, T.</creatorcontrib><creatorcontrib>Hashimoto, N.</creatorcontrib><creatorcontrib>Iida, H.</creatorcontrib><creatorcontrib>Kojima, F.</creatorcontrib><creatorcontrib>Motohashi, K.</creatorcontrib><creatorcontrib>Sasaki, K.</creatorcontrib><title>A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A 16-Mb CMOS SRAM using 0.4-/spl mu/m CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm/sup 2/ is fabricated and an address access time of 12.5 ns has been achieved.< ></description><subject>Cache memory</subject><subject>Capacitors</subject><subject>Circuit simulation</subject><subject>CMOS technology</subject><subject>Costs</subject><subject>Delay effects</subject><subject>Random access memory</subject><subject>Redundancy</subject><subject>Supercomputers</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1994</creationdate><recordtype>article</recordtype><recordid>eNo90E1LAzEQBuAgCtYqePaUk3hJTbLJJnssxS-wFKyCt7BNJhrZ3dRki_Tfu7LF0_AyD8PwInTJ6IwxWt2KGde01NURmjApNWGqeD9GE0qZJhWn9BSd5fw1RCE0m6DVHDM-k6TLmJVkucGL5WqN1y_zJf4J_Se2sW1jRyx0fYrBkQ-ILfRpT5p6H3c9ztBlwHW7bYIPkPI5OvF1k-HiMKfo7f7udfFInlcPT4v5M7EFFT2xriqddsxb57gsawpKgqVMiU05_OaspYKpeghWgXYF5yA93wD1viilssUUXY93tyl-7yD3pg3ZQtPUHcRdNlwzxWklB3gzQptizgm82abQ1mlvGDV_jRlhxsYGejXSAAD_7LD8Bdy4ZHI</recordid><startdate>19940401</startdate><enddate>19940401</enddate><creator>Ishibashi, K.</creator><creator>Komiyaji, K.</creator><creator>Morita, S.</creator><creator>Aoto, T.</creator><creator>Ikeda, S.</creator><creator>Asayama, K.</creator><creator>Koike, A.</creator><creator>Yamanaka, T.</creator><creator>Hashimoto, N.</creator><creator>Iida, H.</creator><creator>Kojima, F.</creator><creator>Motohashi, K.</creator><creator>Sasaki, K.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19940401</creationdate><title>A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers</title><author>Ishibashi, K. ; Komiyaji, K. ; Morita, S. ; Aoto, T. ; Ikeda, S. ; Asayama, K. ; Koike, A. ; Yamanaka, T. ; Hashimoto, N. ; Iida, H. ; Kojima, F. ; Motohashi, K. ; Sasaki, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c304t-cd96d8d1fcdd256a0e75ec0174b6001dcc0417ab60c7e8d322e5f2be0ff3657c3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1994</creationdate><topic>Cache memory</topic><topic>Capacitors</topic><topic>Circuit simulation</topic><topic>CMOS technology</topic><topic>Costs</topic><topic>Delay effects</topic><topic>Random access memory</topic><topic>Redundancy</topic><topic>Supercomputers</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ishibashi, K.</creatorcontrib><creatorcontrib>Komiyaji, K.</creatorcontrib><creatorcontrib>Morita, S.</creatorcontrib><creatorcontrib>Aoto, T.</creatorcontrib><creatorcontrib>Ikeda, S.</creatorcontrib><creatorcontrib>Asayama, K.</creatorcontrib><creatorcontrib>Koike, A.</creatorcontrib><creatorcontrib>Yamanaka, T.</creatorcontrib><creatorcontrib>Hashimoto, N.</creatorcontrib><creatorcontrib>Iida, H.</creatorcontrib><creatorcontrib>Kojima, F.</creatorcontrib><creatorcontrib>Motohashi, K.</creatorcontrib><creatorcontrib>Sasaki, K.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ishibashi, K.</au><au>Komiyaji, K.</au><au>Morita, S.</au><au>Aoto, T.</au><au>Ikeda, S.</au><au>Asayama, K.</au><au>Koike, A.</au><au>Yamanaka, T.</au><au>Hashimoto, N.</au><au>Iida, H.</au><au>Kojima, F.</au><au>Motohashi, K.</au><au>Sasaki, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1994-04-01</date><risdate>1994</risdate><volume>29</volume><issue>4</issue><spage>411</spage><epage>418</epage><pages>411-418</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A 16-Mb CMOS SRAM using 0.4-/spl mu/m CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm/sup 2/ is fabricated and an address access time of 12.5 ns has been achieved.< ></abstract><pub>IEEE</pub><doi>10.1109/4.280689</doi><tpages>8</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1994-04, Vol.29 (4), p.411-418 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_280689 |
| source | IEEE Electronic Library (IEL) |
| subjects | Cache memory Capacitors Circuit simulation CMOS technology Costs Delay effects Random access memory Redundancy Supercomputers Voltage |
| title | A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers |
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