An application specific processor for a multi-system navigation receiver

An application specific processor for a multi-system navigation receiver

An application-specific processor for use as the central component for both signal processing and general control tasks of a combined GPS/Loran-C/Omega/MIS navigation receiver is described. It is the first implementation of the transport-triggered Move architecture framework. Vector registers are in...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Aardoom, E., Stravers, P.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Application specific processors
Computer architecture
Digital filters
Filtering
Finite impulse response filter
Frequency
IIR filters
Navigation
Signal processing
Signal processing algorithms
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Beschreibung
Zusammenfassung:An application-specific processor for use as the central component for both signal processing and general control tasks of a combined GPS/Loran-C/Omega/MIS navigation receiver is described. It is the first implementation of the transport-triggered Move architecture framework. Vector registers are included to enhance signal processing performance, resulting in a single-cycle multiply-accumulate operation, without compromising scalar performance. The projected clock frequency of this implementation is 125 MHz for a 180000-transistor, 1.6- mu m C MOS sea-of-gates chip.< >
DOI:10.1109/ICCD.1992.276192