On realistic and efficient scheduling of DSP algorithms onto multiprocessor architectures
Available strategies for static scheduling of DSP algorithms onto multiprocessor (general purpose and DSP-based) systems are discussed. It is found that simplistic interprocessor communication (IPC) modeling and the absence of precedence analysis are major reasons for unrealistic and not always effi...
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| creator | Koch, P. Bagchi, K.K. Hermansen, K. |
| description | Available strategies for static scheduling of DSP algorithms onto multiprocessor (general purpose and DSP-based) systems are discussed. It is found that simplistic interprocessor communication (IPC) modeling and the absence of precedence analysis are major reasons for unrealistic and not always efficient solutions. The authors propose a mapping scheme based on clustering and various realistic scheduling strategies in order to minimize the runtime of the DSP algorithm. The scheme, called NODUST (for NOde DUplication STrategy), incorporates modeling of the target architecture in terms of nonsimplistic IPC times, which makes the solutions more realistic. The NODUST algorithm provides superior speedup and better processor utilizations in all possible cases compared to the results of T. C. Hu (1961). The compile time for the Hu strategy, on the other hand, is lower than that of NODUST. The speedups do not vary significantly when one moves from the M68000 to the ADSP 2101 environment.< > |
| doi_str_mv | 10.1109/ACSSC.1992.269115 |
| format | Conference Proceeding |
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It is found that simplistic interprocessor communication (IPC) modeling and the absence of precedence analysis are major reasons for unrealistic and not always efficient solutions. The authors propose a mapping scheme based on clustering and various realistic scheduling strategies in order to minimize the runtime of the DSP algorithm. The scheme, called NODUST (for NOde DUplication STrategy), incorporates modeling of the target architecture in terms of nonsimplistic IPC times, which makes the solutions more realistic. The NODUST algorithm provides superior speedup and better processor utilizations in all possible cases compared to the results of T. C. Hu (1961). The compile time for the Hu strategy, on the other hand, is lower than that of NODUST. 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It is found that simplistic interprocessor communication (IPC) modeling and the absence of precedence analysis are major reasons for unrealistic and not always efficient solutions. The authors propose a mapping scheme based on clustering and various realistic scheduling strategies in order to minimize the runtime of the DSP algorithm. The scheme, called NODUST (for NOde DUplication STrategy), incorporates modeling of the target architecture in terms of nonsimplistic IPC times, which makes the solutions more realistic. The NODUST algorithm provides superior speedup and better processor utilizations in all possible cases compared to the results of T. C. Hu (1961). The compile time for the Hu strategy, on the other hand, is lower than that of NODUST. The speedups do not vary significantly when one moves from the M68000 to the ADSP 2101 environment.< ></description><subject>Algorithm design and analysis</subject><subject>Computer architecture</subject><subject>Costs</subject><subject>Digital signal processing</subject><subject>Grain size</subject><subject>Optimal scheduling</subject><subject>Parallel processing</subject><subject>Processor scheduling</subject><subject>Scheduling algorithm</subject><subject>Time factors</subject><issn>1058-6393</issn><issn>2576-2303</issn><isbn>0818631600</isbn><isbn>9780818631603</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1992</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkMlOwzAUAC0WiVL6AXDyD6R4ibdjFSggVSpS4MCpcpznxihLZTsH_h6kMpe5zWEQuqdkTSkxj5uqrqs1NYatmTSUigu0YELJgnHCL9Et0VRLTiUhV2hBidCF5IbfoFVK3-SPUtBSqAX62o84gu1DysFhO7YYvA8uwJhxch20cx_GI548fqrfse2PUwy5GxKexjzhYe5zOMXJQUpTxDa6LmRweY6Q7tC1t32C1b-X6HP7_FG9Frv9y1u12RWBqjIXpYKGaSGahpSuBd-AAi2kZsQq04oWQCsjPRjjjS-l8BY0lZ4zJzzjHvgSPZy7AQAOpxgGG38O5yn8F1fjViA</recordid><startdate>1992</startdate><enddate>1992</enddate><creator>Koch, P.</creator><creator>Bagchi, K.K.</creator><creator>Hermansen, K.</creator><general>IEEE Comput. Soc. Press</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1992</creationdate><title>On realistic and efficient scheduling of DSP algorithms onto multiprocessor architectures</title><author>Koch, P. ; Bagchi, K.K. ; Hermansen, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i174t-47eb2855bb04cdefbe7e856820a79d5dee8796fe99f9f465fae816f32c5f23fe3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1992</creationdate><topic>Algorithm design and analysis</topic><topic>Computer architecture</topic><topic>Costs</topic><topic>Digital signal processing</topic><topic>Grain size</topic><topic>Optimal scheduling</topic><topic>Parallel processing</topic><topic>Processor scheduling</topic><topic>Scheduling algorithm</topic><topic>Time factors</topic><toplevel>online_resources</toplevel><creatorcontrib>Koch, P.</creatorcontrib><creatorcontrib>Bagchi, K.K.</creatorcontrib><creatorcontrib>Hermansen, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Koch, P.</au><au>Bagchi, K.K.</au><au>Hermansen, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>On realistic and efficient scheduling of DSP algorithms onto multiprocessor architectures</atitle><btitle>[1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers</btitle><stitle>ACSSC</stitle><date>1992</date><risdate>1992</risdate><spage>651</spage><epage>655 vol.2</epage><pages>651-655 vol.2</pages><issn>1058-6393</issn><eissn>2576-2303</eissn><isbn>0818631600</isbn><isbn>9780818631603</isbn><abstract>Available strategies for static scheduling of DSP algorithms onto multiprocessor (general purpose and DSP-based) systems are discussed. It is found that simplistic interprocessor communication (IPC) modeling and the absence of precedence analysis are major reasons for unrealistic and not always efficient solutions. The authors propose a mapping scheme based on clustering and various realistic scheduling strategies in order to minimize the runtime of the DSP algorithm. The scheme, called NODUST (for NOde DUplication STrategy), incorporates modeling of the target architecture in terms of nonsimplistic IPC times, which makes the solutions more realistic. The NODUST algorithm provides superior speedup and better processor utilizations in all possible cases compared to the results of T. C. Hu (1961). The compile time for the Hu strategy, on the other hand, is lower than that of NODUST. The speedups do not vary significantly when one moves from the M68000 to the ADSP 2101 environment.< ></abstract><pub>IEEE Comput. Soc. Press</pub><doi>10.1109/ACSSC.1992.269115</doi></addata></record> |
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| identifier | ISSN: 1058-6393 |
| ispartof | [1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers, 1992, p.651-655 vol.2 |
| issn | 1058-6393 2576-2303 |
| language | eng |
| recordid | cdi_ieee_primary_269115 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Computer architecture Costs Digital signal processing Grain size Optimal scheduling Parallel processing Processor scheduling Scheduling algorithm Time factors |
| title | On realistic and efficient scheduling of DSP algorithms onto multiprocessor architectures |
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