Design of a 20 MHz 64-tap transversal filter

Design of a 20 MHz 64-tap transversal filter

The authors describe the architecture and design of a high-speed CMOS VLSI filter processor. The internal architecture of the design is pipelined to achieve a sustained 20-MHz data throughput rate. This translates into an effective computational rate of 1.2 billion multiplications (and a similar num...

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Bibliographische Detailangaben
Hauptverfasser: Stearns, C.C., Luthi, D.A., Ruetz, P.A., Ang, P.H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Arithmetic
Computer architecture
Equations
Filtering
Kernel
Nonlinear filters
Process design
Registers
Throughput
Transversal filters
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Beschreibung
Zusammenfassung:The authors describe the architecture and design of a high-speed CMOS VLSI filter processor. The internal architecture of the design is pipelined to achieve a sustained 20-MHz data throughput rate. This translates into an effective computational rate of 1.2 billion multiplications (and a similar number of additions) per second. The chip is reconfigurable for one- and two-dimensional filtering, the total device count is 240000 transistors, and the die size is 1.4 cm*1.4 cm. Tap design, data-flow organization, and clock distribution are discussed.< >
DOI:10.1109/ICCD.1988.25765