A novel design for the construction and startup of an eight inch pilot line
An 8-in wafer line with 0.5- mu m CMOS process technology for DRAM and SRAM pilot production is discussed. The pilot line is expected to achieve: (1) speedy construction and startup with overall duration of 16 months; (2) a class-0.1 clean environment at 0.3- mu m particle testing level; (3) the fle...
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creator | Tseng, B.H.P. Cheng, C.-H. Chen, H.H. Lu, C.Y. Jensen, R. |
description | An 8-in wafer line with 0.5- mu m CMOS process technology for DRAM and SRAM pilot production is discussed. The pilot line is expected to achieve: (1) speedy construction and startup with overall duration of 16 months; (2) a class-0.1 clean environment at 0.3- mu m particle testing level; (3) the flexibility to advance to 0.2- mu m process technology when needed; (4) the flexibility to enlarge the processing capacity to mass production level (if needed) without interrupting pilot line production. Principles of this design are outlined, difficulties encountered on implementation are discussed, solution approaches employed are illustrated, and preliminary startup results are presented.< > |
doi_str_mv | 10.1109/ASMC.1992.253837 |
format | Conference Proceeding |
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Principles of this design are outlined, difficulties encountered on implementation are discussed, solution approaches employed are illustrated, and preliminary startup results are presented.< ></description><identifier>ISBN: 0780307402</identifier><identifier>ISBN: 9780780307407</identifier><identifier>DOI: 10.1109/ASMC.1992.253837</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS process ; CMOS technology ; Construction industry ; Consumer electronics ; Costs ; Isolation technology ; Manufacturing industries ; Random access memory ; Semiconductor device manufacture ; Space technology</subject><ispartof>IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop - ASMC '92 Proceedings, 1992, p.60-65</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/253837$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/253837$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tseng, B.H.P.</creatorcontrib><creatorcontrib>Cheng, C.-H.</creatorcontrib><creatorcontrib>Chen, H.H.</creatorcontrib><creatorcontrib>Lu, C.Y.</creatorcontrib><creatorcontrib>Jensen, R.</creatorcontrib><title>A novel design for the construction and startup of an eight inch pilot line</title><title>IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop - ASMC '92 Proceedings</title><addtitle>ASMC</addtitle><description>An 8-in wafer line with 0.5- mu m CMOS process technology for DRAM and SRAM pilot production is discussed. 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Principles of this design are outlined, difficulties encountered on implementation are discussed, solution approaches employed are illustrated, and preliminary startup results are presented.< ></description><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Construction industry</subject><subject>Consumer electronics</subject><subject>Costs</subject><subject>Isolation technology</subject><subject>Manufacturing industries</subject><subject>Random access memory</subject><subject>Semiconductor device manufacture</subject><subject>Space technology</subject><isbn>0780307402</isbn><isbn>9780780307407</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1992</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0tLxDAURgMiqOPsxVX-wNSbV9MsS_GFIy6c_ZDH7TRS09JkBP-9A-O3OZzNgY-QOwYVY2Ae2s_3rmLG8Ior0Qh9QW5ANyBAS-BXZJ3zF5wmFdRKXJO3lqbpB0caMMdDov200DIg9VPKZTn6EqdEbQo0F7uU40yn_qQU42EoNCY_0DmOU6FjTHhLLns7Zlz_c0V2T4-77mWz_Xh-7drtJjambIRnHpjS3jstPVhuZOBGgQwSRW8RpQbhgg7e1I6janjdg5PScadt3TixIvfnbETE_bzEb7v87s9vxR-TfUrr</recordid><startdate>1992</startdate><enddate>1992</enddate><creator>Tseng, B.H.P.</creator><creator>Cheng, C.-H.</creator><creator>Chen, H.H.</creator><creator>Lu, C.Y.</creator><creator>Jensen, R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1992</creationdate><title>A novel design for the construction and startup of an eight inch pilot line</title><author>Tseng, B.H.P. ; Cheng, C.-H. ; Chen, H.H. ; Lu, C.Y. ; Jensen, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i89t-3c1c0157ccb74c0a294d29504d4e3faee4703bd7dc96b2e5826f0b44b2b7a68b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1992</creationdate><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Construction industry</topic><topic>Consumer electronics</topic><topic>Costs</topic><topic>Isolation technology</topic><topic>Manufacturing industries</topic><topic>Random access memory</topic><topic>Semiconductor device manufacture</topic><topic>Space technology</topic><toplevel>online_resources</toplevel><creatorcontrib>Tseng, B.H.P.</creatorcontrib><creatorcontrib>Cheng, C.-H.</creatorcontrib><creatorcontrib>Chen, H.H.</creatorcontrib><creatorcontrib>Lu, C.Y.</creatorcontrib><creatorcontrib>Jensen, R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tseng, B.H.P.</au><au>Cheng, C.-H.</au><au>Chen, H.H.</au><au>Lu, C.Y.</au><au>Jensen, R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A novel design for the construction and startup of an eight inch pilot line</atitle><btitle>IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop - ASMC '92 Proceedings</btitle><stitle>ASMC</stitle><date>1992</date><risdate>1992</risdate><spage>60</spage><epage>65</epage><pages>60-65</pages><isbn>0780307402</isbn><isbn>9780780307407</isbn><abstract>An 8-in wafer line with 0.5- mu m CMOS process technology for DRAM and SRAM pilot production is discussed. The pilot line is expected to achieve: (1) speedy construction and startup with overall duration of 16 months; (2) a class-0.1 clean environment at 0.3- mu m particle testing level; (3) the flexibility to advance to 0.2- mu m process technology when needed; (4) the flexibility to enlarge the processing capacity to mass production level (if needed) without interrupting pilot line production. Principles of this design are outlined, difficulties encountered on implementation are discussed, solution approaches employed are illustrated, and preliminary startup results are presented.< ></abstract><pub>IEEE</pub><doi>10.1109/ASMC.1992.253837</doi><tpages>6</tpages></addata></record> |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | CMOS process CMOS technology Construction industry Consumer electronics Costs Isolation technology Manufacturing industries Random access memory Semiconductor device manufacture Space technology |
title | A novel design for the construction and startup of an eight inch pilot line |
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