Using VHDL for simulation of SDL specifications

The authors present the use of VHSIC hardware description language (VHDL) for the simulation of Specification and Description Language (SDL) specification. SDL is a standardized graphical specification and description language. It is widely used for specifications of software systems that are based...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Lutter, B., Glunz, W., Rammig, F.J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application software Computer aided software engineering Computer languages Discrete event simulation Hardware design languages Performance analysis Signal processing Software engineering Software systems Telecommunications
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