Enhanced performance of accumulation mode 0.5 mu m CMOS/SOI operated at 300 K and 85 K
A 0.5 mu m fully depleted CMOS on thin SOI (silicon-on-insulator) VLSI technology has been developed for SRAM and logic applications. Using a normally off, accumulation mode SOI device design with the source/drain/substrate having the same doping polarity, the device transconductance, mobility, and...
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| creator | Wang, L.K. Seliskar, J. Bucelot, T. Edenfeld, A. Haddad, N. |
| description | A 0.5 mu m fully depleted CMOS on thin SOI (silicon-on-insulator) VLSI technology has been developed for SRAM and logic applications. Using a normally off, accumulation mode SOI device design with the source/drain/substrate having the same doping polarity, the device transconductance, mobility, and gate delay are improved by 40% over conventional enhancement mode devices. By cooling the devices to liquid nitrogen temperature, both n- and p-channel devices show improvement in mobility and transconductance, reduction of subthreshold slopes, and an increase of breakdown voltages from the floating substrates.< > |
| doi_str_mv | 10.1109/IEDM.1991.235331 |
| format | Conference Proceeding |
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Using a normally off, accumulation mode SOI device design with the source/drain/substrate having the same doping polarity, the device transconductance, mobility, and gate delay are improved by 40% over conventional enhancement mode devices. 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Using a normally off, accumulation mode SOI device design with the source/drain/substrate having the same doping polarity, the device transconductance, mobility, and gate delay are improved by 40% over conventional enhancement mode devices. By cooling the devices to liquid nitrogen temperature, both n- and p-channel devices show improvement in mobility and transconductance, reduction of subthreshold slopes, and an increase of breakdown voltages from the floating substrates.< ></description><subject>CMOS logic circuits</subject><subject>CMOS technology</subject><subject>Cooling</subject><subject>Delay</subject><subject>Doping</subject><subject>Logic devices</subject><subject>Random access memory</subject><subject>Silicon on insulator technology</subject><subject>Transconductance</subject><subject>Very large scale integration</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>0780302435</isbn><isbn>9780780302433</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1991</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkE1Pg0AURSd-JNLq3rh6fwD6HsMwzNIgatM2LNoYd83rMBMxBRoKC_-9mLq6OYtzc3OFeCSMiNAslsXLJiJjKIqlkpKuRBCTSkMk_XktZqgzlBgnUt2IACmVIRnK7sTsfP5GjLUyKhAfRfvFrXUVnFzvu775A-g8sLVjMx55qLsWmq5ygJGCZoQG8k25XWzLJXSTw8Pk8gASEVbAbQWZgtW9uPV8PLuH_5yL3Wuxy9_Ddfm2zJ_XYZ2ZIUz1wShvpinWJxmnllOaAFNtpWTtE5dpa4nJsXYedeLIxDKJD1ZpdorlXDxdamvn3P7U1w33P_vLG_IX_q9OXQ</recordid><startdate>1991</startdate><enddate>1991</enddate><creator>Wang, L.K.</creator><creator>Seliskar, J.</creator><creator>Bucelot, T.</creator><creator>Edenfeld, A.</creator><creator>Haddad, N.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1991</creationdate><title>Enhanced performance of accumulation mode 0.5 mu m CMOS/SOI operated at 300 K and 85 K</title><author>Wang, L.K. ; Seliskar, J. ; Bucelot, T. ; Edenfeld, A. ; Haddad, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i89t-67b95f9275cf48a6ca61275067c33a7f4e87cc1a1ea7ef074e192342bc57ae5a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1991</creationdate><topic>CMOS logic circuits</topic><topic>CMOS technology</topic><topic>Cooling</topic><topic>Delay</topic><topic>Doping</topic><topic>Logic devices</topic><topic>Random access memory</topic><topic>Silicon on insulator technology</topic><topic>Transconductance</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Wang, L.K.</creatorcontrib><creatorcontrib>Seliskar, J.</creatorcontrib><creatorcontrib>Bucelot, T.</creatorcontrib><creatorcontrib>Edenfeld, A.</creatorcontrib><creatorcontrib>Haddad, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wang, L.K.</au><au>Seliskar, J.</au><au>Bucelot, T.</au><au>Edenfeld, A.</au><au>Haddad, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Enhanced performance of accumulation mode 0.5 mu m CMOS/SOI operated at 300 K and 85 K</atitle><btitle>International Electron Devices Meeting 1991 [Technical Digest]</btitle><stitle>IEDM</stitle><date>1991</date><risdate>1991</risdate><spage>679</spage><epage>682</epage><pages>679-682</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>0780302435</isbn><isbn>9780780302433</isbn><abstract>A 0.5 mu m fully depleted CMOS on thin SOI (silicon-on-insulator) VLSI technology has been developed for SRAM and logic applications. Using a normally off, accumulation mode SOI device design with the source/drain/substrate having the same doping polarity, the device transconductance, mobility, and gate delay are improved by 40% over conventional enhancement mode devices. By cooling the devices to liquid nitrogen temperature, both n- and p-channel devices show improvement in mobility and transconductance, reduction of subthreshold slopes, and an increase of breakdown voltages from the floating substrates.< ></abstract><pub>IEEE</pub><doi>10.1109/IEDM.1991.235331</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0163-1918 |
| ispartof | International Electron Devices Meeting 1991 [Technical Digest], 1991, p.679-682 |
| issn | 0163-1918 2156-017X |
| language | eng |
| recordid | cdi_ieee_primary_235331 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS logic circuits CMOS technology Cooling Delay Doping Logic devices Random access memory Silicon on insulator technology Transconductance Very large scale integration |
| title | Enhanced performance of accumulation mode 0.5 mu m CMOS/SOI operated at 300 K and 85 K |
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