A low power 12 b analog-to-digital converter with on-chip precision trimming

A low power 12 b analog-to-digital converter with on-chip precision trimming

The design and performance of a 12 b charge redistribution ADC is described. The architecture is chosen to minimize conversion time and power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a line...

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Bibliographische Detailangaben
Hauptverfasser: deWit, M., Tan, K.S., Hester, R.K.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analog-digital conversion
Calibration
Capacitors
Circuits
Error correction
Fuses
Linearity
Nonvolatile memory
Power dissipation
Production facilities
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Beschreibung
Zusammenfassung:The design and performance of a 12 b charge redistribution ADC is described. The architecture is chosen to minimize conversion time and power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a linear 1 mu m CMOS process. The die area, including the 12 b parallel digital interface is 15 kmil/sup 2/. The power dissipation is under 15 mW, making the energy per conversion only 45 nJ.< >
DOI:10.1109/VLSIC.1992.229272