Optimum Steiner tree generation
Several phases of the VLSI design process use rectilinear Steiner spanning trees in estimating wire length. Since the problem is NP-complete heuristics form the major portion of the collection of algorithms for this problem. Exact solutions are rare and very few have even been implemented. Thus they...
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| creator | Lewis, F.D. Wang Chia-Chi Pong Van Cleave, N. |
| description | Several phases of the VLSI design process use rectilinear Steiner spanning trees in estimating wire length. Since the problem is NP-complete heuristics form the major portion of the collection of algorithms for this problem. Exact solutions are rare and very few have even been implemented. Thus they seem not to be practical. The authors first reduce the feasible solution space so that exact solutions are possible. Then they develop two branch and bound algorithms which achieve exact solutions. Distributing the computation between processors and parallel computation methods are currently being tested in an attempt to extend the size of the problems which can be actually solved.< > |
| doi_str_mv | 10.1109/GLSV.1992.218343 |
| format | Conference Proceeding |
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Since the problem is NP-complete heuristics form the major portion of the collection of algorithms for this problem. Exact solutions are rare and very few have even been implemented. Thus they seem not to be practical. The authors first reduce the feasible solution space so that exact solutions are possible. Then they develop two branch and bound algorithms which achieve exact solutions. Distributing the computation between processors and parallel computation methods are currently being tested in an attempt to extend the size of the problems which can be actually solved.< ></description><identifier>ISBN: 0818626100</identifier><identifier>ISBN: 9780818626104</identifier><identifier>DOI: 10.1109/GLSV.1992.218343</identifier><language>eng</language><publisher>IEEE Comput. Soc. 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Distributing the computation between processors and parallel computation methods are currently being tested in an attempt to extend the size of the problems which can be actually solved.< ></description><subject>Circuit testing</subject><subject>Computer science</subject><subject>Concurrent computing</subject><subject>Distributed computing</subject><subject>Phase estimation</subject><subject>Process design</subject><subject>Routing</subject><subject>Steiner trees</subject><subject>Very large scale integration</subject><subject>Wire</subject><isbn>0818626100</isbn><isbn>9780818626104</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1992</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpjYJAwNNAzNDSw1Hf3CQ7TM7S0NNIzMrQwNjFmZuAysDC0MDMyMzQw4GDgLS7OMgACE1NDS0NLTgZ5_4KSzNzSXIXgktTMvNQihZKi1FSF9FQgM7EkMz-Ph4E1LTGnOJUXSnMzSLm5hjh76GampqbGFxRl5iYWVcZDrDLGKwkA6_IsEQ</recordid><startdate>1992</startdate><enddate>1992</enddate><creator>Lewis, F.D.</creator><creator>Wang Chia-Chi Pong</creator><creator>Van Cleave, N.</creator><general>IEEE Comput. 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Since the problem is NP-complete heuristics form the major portion of the collection of algorithms for this problem. Exact solutions are rare and very few have even been implemented. Thus they seem not to be practical. The authors first reduce the feasible solution space so that exact solutions are possible. Then they develop two branch and bound algorithms which achieve exact solutions. Distributing the computation between processors and parallel computation methods are currently being tested in an attempt to extend the size of the problems which can be actually solved.< ></abstract><pub>IEEE Comput. Soc. Press</pub><doi>10.1109/GLSV.1992.218343</doi></addata></record> |
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| identifier | ISBN: 0818626100 |
| ispartof | [1992] Proceedings of the Second Great Lakes Symposium on VLSI, 1992, p.207-212 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit testing Computer science Concurrent computing Distributed computing Phase estimation Process design Routing Steiner trees Very large scale integration Wire |
| title | Optimum Steiner tree generation |
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