Applications of a mechanistic yield model for MOSIC chips

A mechanistic random-defect yield model has been extended to several CMOS technologies and applied to several types of circuit forms. Inputs to the model include critical geometries for yield analysis obtained from detailed layout analysis, and defect density values obtained from large area test str...

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Bibliographische Detailangaben

1. Verfasser:	Drum, C.M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit testing CMOS integrated circuits CMOS technology Fabrication Geometry Integrated circuit modeling Integrated circuit yield Metallization Semiconductor device modeling Solid modeling
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