Interconnection complexity study for a piggy back WSHP GaAs systolic processor

The impact of interprocessor communication complexity in systolic arrays is considered. These issues are explored in the context of the design for a compact processor capable of processing 1000 billion systolic operations per second. The goal is to realize the processor in a compact wafer scale hybr...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Philhower, R., McDonald, J.F.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Architecture Electronics packaging Fabrication Gallium arsenide Integrated circuit interconnections Signal processing Substrates Systolic arrays Throughput Wiring
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