A probabilistic model for clock skew
A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for...
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| creator | Kugelmass, S.D. Steiglitz, K. |
| description | A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation.< > |
| doi_str_mv | 10.1109/ARRAYS.1988.18091 |
| format | Conference Proceeding |
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The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation.< ></description><identifier>ISBN: 0818688602</identifier><identifier>ISBN: 9780818688607</identifier><identifier>DOI: 10.1109/ARRAYS.1988.18091</identifier><language>eng</language><publisher>IEEE Comput. Soc. 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International Conference on Systolic Arrays</title><addtitle>ARRAYS</addtitle><description>A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation.< ></description><subject>Clocks</subject><subject>Computer science</subject><subject>Equations</subject><subject>Predictive models</subject><subject>Solid modeling</subject><subject>Timing</subject><subject>Topology</subject><subject>Upper bound</subject><subject>Very large scale integration</subject><subject>Wire</subject><isbn>0818688602</isbn><isbn>9780818688607</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1988</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKAzEUQAMiVGs_oLss3M54702aSZZD8VEoCK0bV-XmBbFTpkwK4t8r6tmc3YEjxBKhRQT30O92_fu-RWdtixYcXolbsGiNtQZoJha1fsAPWqsO6Ubc9_I8jZ59GUq9lCBPY0yDzOMkwzCGo6zH9HknrjMPNS3-PRf7p8e39UuzfX3erPttU6y5NI6IISqtiNkQOAC0HiJ5r51Z-ZhYZW2YupjJaWIXkDqXcjDgM5Gai-VftaSUDuepnHj6OvxOqG8oRjwF</recordid><startdate>1988</startdate><enddate>1988</enddate><creator>Kugelmass, S.D.</creator><creator>Steiglitz, K.</creator><general>IEEE Comput. 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Press</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1988</creationdate><title>A probabilistic model for clock skew</title><author>Kugelmass, S.D. ; Steiglitz, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i86t-922a0d3432aa62090018b0d2bb4965bdea3f46a27df2942a9c1279efc60bf223</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1988</creationdate><topic>Clocks</topic><topic>Computer science</topic><topic>Equations</topic><topic>Predictive models</topic><topic>Solid modeling</topic><topic>Timing</topic><topic>Topology</topic><topic>Upper bound</topic><topic>Very large scale integration</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Kugelmass, S.D.</creatorcontrib><creatorcontrib>Steiglitz, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kugelmass, S.D.</au><au>Steiglitz, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A probabilistic model for clock skew</atitle><btitle>[1988] Proceedings. International Conference on Systolic Arrays</btitle><stitle>ARRAYS</stitle><date>1988</date><risdate>1988</risdate><spage>545</spage><epage>554</epage><pages>545-554</pages><isbn>0818688602</isbn><isbn>9780818688607</isbn><abstract>A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation.< ></abstract><pub>IEEE Comput. Soc. Press</pub><doi>10.1109/ARRAYS.1988.18091</doi><tpages>10</tpages></addata></record> |
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| ispartof | [1988] Proceedings. International Conference on Systolic Arrays, 1988, p.545-554 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Computer science Equations Predictive models Solid modeling Timing Topology Upper bound Very large scale integration Wire |
| title | A probabilistic model for clock skew |
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