High-speed, low-voltage complementary heterostructure FET circuit technology
A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth Al...
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| creator | Kiehl, R.A. Yates, J. Palmateer, L.F. Wright, S.L. Frank, D.J. Jackson, T.N. Degelormo, J.F. Fleischman, A.J. |
| description | A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs-GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 mu m gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.< > |
| doi_str_mv | 10.1109/GAAS.1991.172644 |
| format | Conference Proceeding |
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This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs-GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 mu m gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.< ></description><identifier>ISBN: 9780780301962</identifier><identifier>ISBN: 078030196X</identifier><identifier>DOI: 10.1109/GAAS.1991.172644</identifier><language>eng</language><publisher>IEEE</publisher><subject>Annealing ; Circuit testing ; Doping ; Epitaxial growth ; Fabrication ; FET circuits ; Gallium arsenide ; Impurities ; Integrated circuit technology ; Transconductance</subject><ispartof>[1991] GaAs IC Symposium Technical Digest, 1991, p.101-104</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/172644$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/172644$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kiehl, R.A.</creatorcontrib><creatorcontrib>Yates, J.</creatorcontrib><creatorcontrib>Palmateer, L.F.</creatorcontrib><creatorcontrib>Wright, S.L.</creatorcontrib><creatorcontrib>Frank, D.J.</creatorcontrib><creatorcontrib>Jackson, T.N.</creatorcontrib><creatorcontrib>Degelormo, J.F.</creatorcontrib><creatorcontrib>Fleischman, A.J.</creatorcontrib><title>High-speed, low-voltage complementary heterostructure FET circuit technology</title><title>[1991] GaAs IC Symposium Technical Digest</title><addtitle>GAAS</addtitle><description>A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. 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This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs-GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 mu m gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.< ></abstract><pub>IEEE</pub><doi>10.1109/GAAS.1991.172644</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9780780301962 |
| ispartof | [1991] GaAs IC Symposium Technical Digest, 1991, p.101-104 |
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| language | eng |
| recordid | cdi_ieee_primary_172644 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Annealing Circuit testing Doping Epitaxial growth Fabrication FET circuits Gallium arsenide Impurities Integrated circuit technology Transconductance |
| title | High-speed, low-voltage complementary heterostructure FET circuit technology |
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