An Area-Efficient Variable Length Decoder IP Core Design for MPEG- hbox 1/2/4Video Coding Applications

This paper proposes an area-efficient variable length decoder (VLD) IP core design for MPEG-1/2/4 video coding applications. The proposed IP core exploits the parallel numerical matching in the MPEG-1/2/4 entropy decoding to achieve high data throughput rate in terms of limited hardware cost. This f...

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Veröffentlicht in:	IEEE transactions on circuits and systems for video technology 2006-09, Vol.16 (9), p.1172-1178
Hauptverfasser:	Chih-Da Chien, Keng-Po Lu, Yu-Min Chen, Jiun-In Guo, Yuan-Sun Chu, Ching-Lung Su
Format:	Artikel
Sprache:	eng
Schlagworte:	Clocks CMOS technology Costs Decoding Energy consumption Entropy Hardware Low-power design MPEG Throughput variable length decoder (VLD) Video coding Voltage
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