High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Young's modulus (YM) offset spacer covered with dual stress liner (DSL), were used for...

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Bibliographische Detailangaben

Hauptverfasser:	Sugii, T., Hashimoto, K., Miyajima, M., Sato, S., Kojima, M., Nakai, S., Fukuyama, S., Nakaishi, M., Sukegawa, K., Aoyama, T., Tamura, N., Fukutome, H., Miyashita, T., Sakuma, T., Ota, H., Katakami, A., Shimamune, Y., Hatada, A., Minakata, H., Hayami, Y., Mori, T., Okoshi, K., Isome, T., Watanabe, T., Morioka, H., Kokura, H., Ogura, J., Sugimoto, K., Owada, T., Okuno, M., Pidin, S., Kawamura, K., Sakoda, T., Yamaguchi, A., Okabe, K., Shima, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitive sensors Charge carrier processes Compressive stress DSL Electron mobility Laboratories Leakage current MOS devices Power transistors Tensile stress
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