Improved First-Order Time-Delay Tanlock Loop Architectures
This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switch...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2006-09, Vol.53 (9), p.1896-1908 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1908 |
|---|---|
| container_issue | 9 |
| container_start_page | 1896 |
| container_title | IEEE transactions on circuits and systems. 1, Fundamental theory and applications |
| container_volume | 53 |
| creator | Al-Qutayri, M.A. Al-Araji, S.R. Al-Moosa, N.I. |
| description | This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation |
| doi_str_mv | 10.1109/TCSI.2006.880316 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_1703775</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1703775</ieee_id><sourcerecordid>889421233</sourcerecordid><originalsourceid>FETCH-LOGICAL-c322t-a9a027d11b46f1bd3fd29cc0f926ceb78594a04b75e1e36feca50fc5531d9a473</originalsourceid><addsrcrecordid>eNpdkEtLw0AUhYMoWB97wU1w4yr1zkzm5a5Uq4VCF8b1MJncYGrS1JlE6L83IYLg6t7Fdw6HL4puCMwJAf2QLd_Wcwog5koBI-IkmhHOVQIKxOn4pzpRjKrz6CKEHQDVAzWLHtfNwbffWMSryocu2foCfZxVDSZPWNtjnNl93brPeNO2h3jh3UfVoet6j-EqOittHfD6915G76vnbPmabLYv6-VikzhGaZdYbYHKgpA8FSXJC1YWVDsHpabCYS4V16mFNJccCTJRorMcSsc5I4W2qWSX0f3UOwz96jF0pqmCw7q2e2z7YJTSKSWUsYG8-0fu2t7vh3FGCUm1YoIMEEyQ820IHktz8FVj_dEQMKNKM6o0o0ozqRwit1OkQsQ_XAKTkrMfQNFueA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>867298361</pqid></control><display><type>article</type><title>Improved First-Order Time-Delay Tanlock Loop Architectures</title><source>IEEE Electronic Library (IEL)</source><creator>Al-Qutayri, M.A. ; Al-Araji, S.R. ; Al-Moosa, N.I.</creator><creatorcontrib>Al-Qutayri, M.A. ; Al-Araji, S.R. ; Al-Moosa, N.I.</creatorcontrib><description>This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation</description><identifier>ISSN: 1549-8328</identifier><identifier>ISSN: 1057-7122</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2006.880316</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Architecture ; Circuits ; Delay ; Demodulation ; Design engineering ; Disturbances ; Field programmable gate arrays ; Frequency ; Gain ; loop ; Mobile communication ; Performance gain ; Phase locked loops ; Resilience ; Sampling methods ; Simulation ; tanlock</subject><ispartof>IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-09, Vol.53 (9), p.1896-1908</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c322t-a9a027d11b46f1bd3fd29cc0f926ceb78594a04b75e1e36feca50fc5531d9a473</citedby><cites>FETCH-LOGICAL-c322t-a9a027d11b46f1bd3fd29cc0f926ceb78594a04b75e1e36feca50fc5531d9a473</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1703775$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54737</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1703775$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Al-Qutayri, M.A.</creatorcontrib><creatorcontrib>Al-Araji, S.R.</creatorcontrib><creatorcontrib>Al-Moosa, N.I.</creatorcontrib><title>Improved First-Order Time-Delay Tanlock Loop Architectures</title><title>IEEE transactions on circuits and systems. 1, Fundamental theory and applications</title><addtitle>TCSI</addtitle><description>This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation</description><subject>Architecture</subject><subject>Circuits</subject><subject>Delay</subject><subject>Demodulation</subject><subject>Design engineering</subject><subject>Disturbances</subject><subject>Field programmable gate arrays</subject><subject>Frequency</subject><subject>Gain</subject><subject>loop</subject><subject>Mobile communication</subject><subject>Performance gain</subject><subject>Phase locked loops</subject><subject>Resilience</subject><subject>Sampling methods</subject><subject>Simulation</subject><subject>tanlock</subject><issn>1549-8328</issn><issn>1057-7122</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLw0AUhYMoWB97wU1w4yr1zkzm5a5Uq4VCF8b1MJncYGrS1JlE6L83IYLg6t7Fdw6HL4puCMwJAf2QLd_Wcwog5koBI-IkmhHOVQIKxOn4pzpRjKrz6CKEHQDVAzWLHtfNwbffWMSryocu2foCfZxVDSZPWNtjnNl93brPeNO2h3jh3UfVoet6j-EqOittHfD6915G76vnbPmabLYv6-VikzhGaZdYbYHKgpA8FSXJC1YWVDsHpabCYS4V16mFNJccCTJRorMcSsc5I4W2qWSX0f3UOwz96jF0pqmCw7q2e2z7YJTSKSWUsYG8-0fu2t7vh3FGCUm1YoIMEEyQ820IHktz8FVj_dEQMKNKM6o0o0ozqRwit1OkQsQ_XAKTkrMfQNFueA</recordid><startdate>20060901</startdate><enddate>20060901</enddate><creator>Al-Qutayri, M.A.</creator><creator>Al-Araji, S.R.</creator><creator>Al-Moosa, N.I.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20060901</creationdate><title>Improved First-Order Time-Delay Tanlock Loop Architectures</title><author>Al-Qutayri, M.A. ; Al-Araji, S.R. ; Al-Moosa, N.I.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c322t-a9a027d11b46f1bd3fd29cc0f926ceb78594a04b75e1e36feca50fc5531d9a473</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Architecture</topic><topic>Circuits</topic><topic>Delay</topic><topic>Demodulation</topic><topic>Design engineering</topic><topic>Disturbances</topic><topic>Field programmable gate arrays</topic><topic>Frequency</topic><topic>Gain</topic><topic>loop</topic><topic>Mobile communication</topic><topic>Performance gain</topic><topic>Phase locked loops</topic><topic>Resilience</topic><topic>Sampling methods</topic><topic>Simulation</topic><topic>tanlock</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Al-Qutayri, M.A.</creatorcontrib><creatorcontrib>Al-Araji, S.R.</creatorcontrib><creatorcontrib>Al-Moosa, N.I.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on circuits and systems. 1, Fundamental theory and applications</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Al-Qutayri, M.A.</au><au>Al-Araji, S.R.</au><au>Al-Moosa, N.I.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Improved First-Order Time-Delay Tanlock Loop Architectures</atitle><jtitle>IEEE transactions on circuits and systems. 1, Fundamental theory and applications</jtitle><stitle>TCSI</stitle><date>2006-09-01</date><risdate>2006</risdate><volume>53</volume><issue>9</issue><spage>1896</spage><epage>1908</epage><pages>1896-1908</pages><issn>1549-8328</issn><issn>1057-7122</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2006.880316</doi><tpages>13</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1549-8328 |
| ispartof | IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-09, Vol.53 (9), p.1896-1908 |
| issn | 1549-8328 1057-7122 1558-0806 |
| language | eng |
| recordid | cdi_ieee_primary_1703775 |
| source | IEEE Electronic Library (IEL) |
| subjects | Architecture Circuits Delay Demodulation Design engineering Disturbances Field programmable gate arrays Frequency Gain loop Mobile communication Performance gain Phase locked loops Resilience Sampling methods Simulation tanlock |
| title | Improved First-Order Time-Delay Tanlock Loop Architectures |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T05%3A16%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Improved%20First-Order%20Time-Delay%20Tanlock%20Loop%20Architectures&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%201,%20Fundamental%20theory%20and%20applications&rft.au=Al-Qutayri,%20M.A.&rft.date=2006-09-01&rft.volume=53&rft.issue=9&rft.spage=1896&rft.epage=1908&rft.pages=1896-1908&rft.issn=1549-8328&rft.eissn=1558-0806&rft.coden=ITCSCH&rft_id=info:doi/10.1109/TCSI.2006.880316&rft_dat=%3Cproquest_RIE%3E889421233%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=867298361&rft_id=info:pmid/&rft_ieee_id=1703775&rfr_iscdi=true |