Via placement for minimum interconnect delay in three-dimensional (3D) circuits
The propagation delay of interlayer 3D interconnects is investigated in this paper. For RC interconnects connecting two circuits located on different physical planes, the interconnect delay is minimized by optimally placing the non-stacked interlayer vias. The problem of determining this optimum via...
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| creator | Pavlidis, V.F. Friedman, E.G. |
| description | The propagation delay of interlayer 3D interconnects is investigated in this paper. For RC interconnects connecting two circuits located on different physical planes, the interconnect delay is minimized by optimally placing the non-stacked interlayer vias. The problem of determining this optimum via locations under the Elmore delay model is described as a geometric program. Simulations indicate delay improvements of up to 26% for relatively short interconnect. The proposed approach is also compared with a wire sizing algorithm. Timing-driven via placement exhibits better results both in terms of delay and power consumption |
| doi_str_mv | 10.1109/ISCAS.2006.1693651 |
| format | Conference Proceeding |
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For RC interconnects connecting two circuits located on different physical planes, the interconnect delay is minimized by optimally placing the non-stacked interlayer vias. The problem of determining this optimum via locations under the Elmore delay model is described as a geometric program. Simulations indicate delay improvements of up to 26% for relatively short interconnect. The proposed approach is also compared with a wire sizing algorithm. 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For RC interconnects connecting two circuits located on different physical planes, the interconnect delay is minimized by optimally placing the non-stacked interlayer vias. The problem of determining this optimum via locations under the Elmore delay model is described as a geometric program. Simulations indicate delay improvements of up to 26% for relatively short interconnect. The proposed approach is also compared with a wire sizing algorithm. Timing-driven via placement exhibits better results both in terms of delay and power consumption</description><subject>Contracts</subject><subject>Impedance</subject><subject>Inorganic materials</subject><subject>Integrated circuit interconnections</subject><subject>Predictive models</subject><subject>Propagation delay</subject><subject>Routing</subject><subject>Semiconductor device modeling</subject><subject>Solid modeling</subject><subject>Wire</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>0780393899</isbn><isbn>9780780393899</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUMlqwzAUFF2gbpofaC86tge770nyomNwt0Agh7S9Bll6piq2HGTnkL-voZnLMMMwMMPYPUKGCPp5vatXu0wAFBkWWhY5XrBEYF6lmIv8kt1CWYHUstL6iiUgSkyVBHHDluP4CzNUPmtI2PbbG37ojKWewsTbIfLeB98fe-7DRNEOIZCduKPOnGaLTz-RKHV-jo9-CKbjj_LliVsf7dFP4x27bk030vLMC_b19vpZf6Sb7fu6Xm1SjyVOaSNQlcYqkJVT4IQyLTYObSVdiaawrskJoSBthFTCatmKthKk9bzVWSS5YA__vZ6I9ofoexNP-_MX8g9eB1Df</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Pavlidis, V.F.</creator><creator>Friedman, E.G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2006</creationdate><title>Via placement for minimum interconnect delay in three-dimensional (3D) circuits</title><author>Pavlidis, V.F. ; Friedman, E.G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i171t-b2147ac4038d40d24af1bd1c83d71a6cdb5e106e9a2342c93f2f82e99936dc1e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2006</creationdate><topic>Contracts</topic><topic>Impedance</topic><topic>Inorganic materials</topic><topic>Integrated circuit interconnections</topic><topic>Predictive models</topic><topic>Propagation delay</topic><topic>Routing</topic><topic>Semiconductor device modeling</topic><topic>Solid modeling</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Pavlidis, V.F.</creatorcontrib><creatorcontrib>Friedman, E.G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pavlidis, V.F.</au><au>Friedman, E.G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Via placement for minimum interconnect delay in three-dimensional (3D) circuits</atitle><btitle>2006 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2006</date><risdate>2006</risdate><spage>4 pp.</spage><epage>4590</epage><pages>4 pp.-4590</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>0780393899</isbn><isbn>9780780393899</isbn><abstract>The propagation delay of interlayer 3D interconnects is investigated in this paper. For RC interconnects connecting two circuits located on different physical planes, the interconnect delay is minimized by optimally placing the non-stacked interlayer vias. The problem of determining this optimum via locations under the Elmore delay model is described as a geometric program. Simulations indicate delay improvements of up to 26% for relatively short interconnect. The proposed approach is also compared with a wire sizing algorithm. Timing-driven via placement exhibits better results both in terms of delay and power consumption</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2006.1693651</doi></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Contracts Impedance Inorganic materials Integrated circuit interconnections Predictive models Propagation delay Routing Semiconductor device modeling Solid modeling Wire |
| title | Via placement for minimum interconnect delay in three-dimensional (3D) circuits |
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