An improved frequency and phase synthesis architecture
A ring oscillator normally has multiple phase outputs which can be programmed into different frequencies with adjustable phase. This idea is implemented into "flying-adder" architecture (Mair and Xiu, 2000). However, this architecture has a timing violation issue and the phase synthesis ra...
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| creator | Gonggui Xu Shouli Yan |
| description | A ring oscillator normally has multiple phase outputs which can be programmed into different frequencies with adjustable phase. This idea is implemented into "flying-adder" architecture (Mair and Xiu, 2000). However, this architecture has a timing violation issue and the phase synthesis range only covers half cycle of the output clock. This paper proposed an improved architecture in which these problems are solved and the phase synthesis range is expanded from half clock cycle into full clock cycle. Compared to the prior art (Mair and Xiu, 2000), the improved architecture is much more practical |
| doi_str_mv | 10.1109/ISCAS.2006.1693548 |
| format | Conference Proceeding |
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This idea is implemented into "flying-adder" architecture (Mair and Xiu, 2000). However, this architecture has a timing violation issue and the phase synthesis range only covers half cycle of the output clock. This paper proposed an improved architecture in which these problems are solved and the phase synthesis range is expanded from half clock cycle into full clock cycle. Compared to the prior art (Mair and Xiu, 2000), the improved architecture is much more practical</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 0780393899</identifier><identifier>ISBN: 9780780393899</identifier><identifier>EISSN: 2158-1525</identifier><identifier>DOI: 10.1109/ISCAS.2006.1693548</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Computer architecture ; Delay ; Frequency synthesizers ; Instruments ; Ring oscillators ; Signal generators ; Timing ; Voltage-controlled oscillators</subject><ispartof>2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1693548$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1693548$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gonggui Xu</creatorcontrib><creatorcontrib>Shouli Yan</creatorcontrib><title>An improved frequency and phase synthesis architecture</title><title>2006 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>A ring oscillator normally has multiple phase outputs which can be programmed into different frequencies with adjustable phase. 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Compared to the prior art (Mair and Xiu, 2000), the improved architecture is much more practical</description><subject>Clocks</subject><subject>Computer architecture</subject><subject>Delay</subject><subject>Frequency synthesizers</subject><subject>Instruments</subject><subject>Ring oscillators</subject><subject>Signal generators</subject><subject>Timing</subject><subject>Voltage-controlled oscillators</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>0780393899</isbn><isbn>9780780393899</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jr0OgjAURm_8ScSfF9ClLwDethTbkRiNzribBq-hRhFbMOHtdXD2W05OzvIBLDkmnKNZH4ttXiQCMUt4ZqRK9QAiwZWOuRJqCFPcaJRGamNGEKHY8DiVKCawCOGG36Xq6xhBltfMPRr_fNOFXT29OqrLntn6wprKBmKhr9uKggvM-rJyLZVt52kO46u9B1r8OIPVfnfaHmJHROfGu4f1_fl3Tf6vH7LMOZc</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Gonggui Xu</creator><creator>Shouli Yan</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2006</creationdate><title>An improved frequency and phase synthesis architecture</title><author>Gonggui Xu ; Shouli Yan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_16935483</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Clocks</topic><topic>Computer architecture</topic><topic>Delay</topic><topic>Frequency synthesizers</topic><topic>Instruments</topic><topic>Ring oscillators</topic><topic>Signal generators</topic><topic>Timing</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Gonggui Xu</creatorcontrib><creatorcontrib>Shouli Yan</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gonggui Xu</au><au>Shouli Yan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An improved frequency and phase synthesis architecture</atitle><btitle>2006 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2006</date><risdate>2006</risdate><spage>4 pp.</spage><pages>4 pp.-</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>0780393899</isbn><isbn>9780780393899</isbn><abstract>A ring oscillator normally has multiple phase outputs which can be programmed into different frequencies with adjustable phase. This idea is implemented into "flying-adder" architecture (Mair and Xiu, 2000). However, this architecture has a timing violation issue and the phase synthesis range only covers half cycle of the output clock. This paper proposed an improved architecture in which these problems are solved and the phase synthesis range is expanded from half clock cycle into full clock cycle. Compared to the prior art (Mair and Xiu, 2000), the improved architecture is much more practical</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2006.1693548</doi></addata></record> |
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| identifier | ISSN: 0271-4302 |
| ispartof | 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp. |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_1693548 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Computer architecture Delay Frequency synthesizers Instruments Ring oscillators Signal generators Timing Voltage-controlled oscillators |
| title | An improved frequency and phase synthesis architecture |
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