Weighted-to-residue and residue-to-weighted converters with three-moduli (2/sup n/ - 1, 2/sup n/, 2/sup n/+1) signed-digit architectures

In this paper, high-speed signed-digit (SD) architectures for weighted-to-residue (WTOR) and residue-to-weighted (RTOW) conversion with the moduli set (2 n - 1, 2 n , 2 n +1) are proposed. The complexity of the conversion has been greatly reduced by using compact forms for the multiplicative inverse...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Shuangching Chen, Shugang Wei
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders Arithmetic Circuit simulation Circuit synthesis Computer architecture Computer science Digital filters Hardware Information management Modular construction
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