Weighted-to-residue and residue-to-weighted converters with three-moduli (2/sup n/ - 1, 2/sup n/, 2/sup n/+1) signed-digit architectures
In this paper, high-speed signed-digit (SD) architectures for weighted-to-residue (WTOR) and residue-to-weighted (RTOW) conversion with the moduli set (2 n - 1, 2 n , 2 n +1) are proposed. The complexity of the conversion has been greatly reduced by using compact forms for the multiplicative inverse...
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| creator | Shuangching Chen Shugang Wei |
| description | In this paper, high-speed signed-digit (SD) architectures for weighted-to-residue (WTOR) and residue-to-weighted (RTOW) conversion with the moduli set (2 n - 1, 2 n , 2 n +1) are proposed. The complexity of the conversion has been greatly reduced by using compact forms for the multiplicative inverse and the properties of modular arithmetic. The simple relationships of WTOR and RTOW result in simpler hardware requirements for the converters. The primary advantages of our method is that our conversions utilize the modulo m signed-digit adder (MSDA) only and the constructions are simple. We also investigate the modular arithmetic between binary and SD number representation by circuit design and simulation, and the results show the importance of SD architectures for WTOR and RTOW |
| doi_str_mv | 10.1109/ISCAS.2006.1693347 |
| format | Conference Proceeding |
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The complexity of the conversion has been greatly reduced by using compact forms for the multiplicative inverse and the properties of modular arithmetic. The simple relationships of WTOR and RTOW result in simpler hardware requirements for the converters. The primary advantages of our method is that our conversions utilize the modulo m signed-digit adder (MSDA) only and the constructions are simple. We also investigate the modular arithmetic between binary and SD number representation by circuit design and simulation, and the results show the importance of SD architectures for WTOR and RTOW</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 0780393899</identifier><identifier>ISBN: 9780780393899</identifier><identifier>EISSN: 2158-1525</identifier><identifier>DOI: 10.1109/ISCAS.2006.1693347</identifier><language>eng</language><publisher>IEEE</publisher><subject>Adders ; Arithmetic ; Circuit simulation ; Circuit synthesis ; Computer architecture ; Computer science ; Digital filters ; Hardware ; Information management ; Modular construction</subject><ispartof>2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1693347$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,4035,4036,27904,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1693347$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Shuangching Chen</creatorcontrib><creatorcontrib>Shugang Wei</creatorcontrib><title>Weighted-to-residue and residue-to-weighted converters with three-moduli (2/sup n/ - 1, 2/sup n/, 2/sup n/+1) signed-digit architectures</title><title>2006 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>In this paper, high-speed signed-digit (SD) architectures for weighted-to-residue (WTOR) and residue-to-weighted (RTOW) conversion with the moduli set (2 n - 1, 2 n , 2 n +1) are proposed. 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The complexity of the conversion has been greatly reduced by using compact forms for the multiplicative inverse and the properties of modular arithmetic. The simple relationships of WTOR and RTOW result in simpler hardware requirements for the converters. The primary advantages of our method is that our conversions utilize the modulo m signed-digit adder (MSDA) only and the constructions are simple. We also investigate the modular arithmetic between binary and SD number representation by circuit design and simulation, and the results show the importance of SD architectures for WTOR and RTOW</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2006.1693347</doi></addata></record> |
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| identifier | ISSN: 0271-4302 |
| ispartof | 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp. |
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| language | eng |
| recordid | cdi_ieee_primary_1693347 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Adders Arithmetic Circuit simulation Circuit synthesis Computer architecture Computer science Digital filters Hardware Information management Modular construction |
| title | Weighted-to-residue and residue-to-weighted converters with three-moduli (2/sup n/ - 1, 2/sup n/, 2/sup n/+1) signed-digit architectures |
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