Design Space Exploration for Rapid Development of DSP Applications
In this paper a new methodology for accelerating the development cycle of DSP applications is presented. This methodology is composed of three steps 1) algorithm design with Matlab (mathworks), 2) algorithmic-level characterization and parallelism exploration using Design-Trotter SoC framework (LEST...
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| creator | Le Moullec, Y. Christensen, S.S. Chenpeng, W. Koch, P. Bilavarn, S. |
| description | In this paper a new methodology for accelerating the development cycle of DSP applications is presented. This methodology is composed of three steps 1) algorithm design with Matlab (mathworks), 2) algorithmic-level characterization and parallelism exploration using Design-Trotter SoC framework (LESTER/CISS) and 3) FPGA hardware synthesis with DK Design Suite (Celoxica). We have applied the proposed methodology to explore the design space of a RAKE receiver. The results show that by using this methodology, designers can rapidly converge from specification phases to the final synthesis of the system. The parallelism information provided by Design-Trotter has been shown extremely useful to develop the Handel-C description of the application, enabling a rapid synthesis of the system with DK Design Suite. The time-to-market factor is thus significantly reduced |
| doi_str_mv | 10.1109/ICICS.2005.1689289 |
| format | Conference Proceeding |
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This methodology is composed of three steps 1) algorithm design with Matlab (mathworks), 2) algorithmic-level characterization and parallelism exploration using Design-Trotter SoC framework (LESTER/CISS) and 3) FPGA hardware synthesis with DK Design Suite (Celoxica). We have applied the proposed methodology to explore the design space of a RAKE receiver. The results show that by using this methodology, designers can rapidly converge from specification phases to the final synthesis of the system. The parallelism information provided by Design-Trotter has been shown extremely useful to develop the Handel-C description of the application, enabling a rapid synthesis of the system with DK Design Suite. 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This methodology is composed of three steps 1) algorithm design with Matlab (mathworks), 2) algorithmic-level characterization and parallelism exploration using Design-Trotter SoC framework (LESTER/CISS) and 3) FPGA hardware synthesis with DK Design Suite (Celoxica). We have applied the proposed methodology to explore the design space of a RAKE receiver. The results show that by using this methodology, designers can rapidly converge from specification phases to the final synthesis of the system. The parallelism information provided by Design-Trotter has been shown extremely useful to develop the Handel-C description of the application, enabling a rapid synthesis of the system with DK Design Suite. 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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Acceleration Algorithm design and analysis Design methodology Design Space Exploration Digital signal processing Fading Field programmable gate arrays Hardware Implementation Multipath channels Space exploration Time to market |
| title | Design Space Exploration for Rapid Development of DSP Applications |
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